Problems and challenges of emerging technology networks− on− chip: A review

AB Achballah, SB Othman, SB Saoud - Microprocessors and Microsystems, 2017 - Elsevier
Abstract Networks− on− chip (NoC) are an alternative to alleviate the problems of legacy
interconnect fabrics. However, many emerging technology NoC are developed and are now …

A resilient routing algorithm with formal reliability analysis for partially connected 3D-NoCs

R Salamat, M Khayambashi, M Ebrahimi… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
3D ICs can take advantage of a scalable communication platform, commonly referred to as
the Networks-on-Chip (NoC). In the basic form of 3D-NoC, all routers are vertically …

Impact of electrostatic coupling on monolithic 3D-enabled network on chip

D Lee, S Das, JR Doppa, PP Pande… - ACM Transactions on …, 2019 - dl.acm.org
Monolithic-3D-integration (M3D) improves the performance and energy efficiency of 3D ICs
over conventional through-silicon-vias-based counterparts. The smaller dimensions of …

Three-dimensional NoC reliability evaluation

A Eghbal, PM Yaghini, N Bagherzadeh - US Patent 11,093,673, 2021 - Google Patents
Methods, storage mediums, and apparatuses for evaluating the reliability of Three-
Dimensional (3D) Network-on-Chip (NoC) designs are described. The described …

A comprehensive reliability assessment of fault-resilient network-on-chip using analytical model

KN Dang, AB Ahmed, XT Tran… - … Transactions on Very …, 2017 - ieeexplore.ieee.org
The component's failure in network-on-chips (NoCs) has been a critical factor on the
system's reliability. In order to alleviate the impact of faults, fault tolerance has been …

3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs

Z Shirmohammadi, HZ Sabzi… - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
One of the cost-efficient fabrication approaches for connecting layers in three-dimensional
integrated circuits (3D ICs) is the use of through-silicon vias (TSVs). However, the large and …

RLARA: A TSV-Aware Reinforcement Learning Assisted Fault-Tolerant Routing Algorithm for 3D Network-on-Chip

J Jiao, R Shen, L Chen, J Liu, D Han - Electronics, 2023 - mdpi.com
A three-dimensional Network-on-Chip (3D NoC) equips modern multicore processors with
good scalability, a small area, and high performance using vertical through-silicon vias …

[PDF][PDF] An extensive review of emerging technology networks-on-chip proposals

AB Achballah, SB Othman… - Global J. Res. Eng., Elect …, 2017 - researchgate.net
Many synthesis works discussed emerging technology networks− on− chip (NoC) from
different aspects. These works were and still are a solid foundation of the state of the art for …

Reliability-and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation

W Gao, Z Qian, P Zhou - Integration, 2019 - Elsevier
Abstract Network-on-Chip (NoC)-based communication architecture is promising in
addressing the communication bottlenecks in current and future multicore processors. In this …

Reliability assessment of fault tolerant routing algorithms in networks-on-chip: An analytic approach

S Moriam, GP Fettweis - Design, Automation & Test in Europe …, 2017 - ieeexplore.ieee.org
Rapid scaling of transistor gate sizes has significantly increased the density of on-chip
integrations and paved the way for many-core systems-on-chip with highly improved …