ScaleHLS: a scalable high-level synthesis framework with multi-level transformations and optimizations
H Ye, HG Jun, H Jeong, S Neuendorffer… - Proceedings of the 59th …, 2022 - dl.acm.org
This paper presents an enhanced version of a scalable HLS (High-Level Synthesis)
framework named ScaleHLS, which can compile HLS C/C++ programs and PyTorch models …
framework named ScaleHLS, which can compile HLS C/C++ programs and PyTorch models …
Autoscaledse: A scalable design space exploration engine for high-level synthesis
High-Level Synthesis (HLS) has enabled users to rapidly develop designs targeted for
FPGAs from the behavioral description of the design. However, to synthesize an optimal …
FPGAs from the behavioral description of the design. However, to synthesize an optimal …
Machine learning for FPGA electronic design automation
A Biscontini, E Popovici, A Temko - IEEE Access, 2024 - ieeexplore.ieee.org
In the last decades, field-programmable gate arrays (FPGAs) have become increasingly
important to the electronics industry, offering higher performance and lower power …
important to the electronics industry, offering higher performance and lower power …
HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
Dataflow architectures are growing in popularity due to their potential to mitigate the
challenges posed by the memory wall inherent to the Von Neumann architecture. At the …
challenges posed by the memory wall inherent to the Von Neumann architecture. At the …
Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach
High-level synthesis, source-to-source compilers, and various Design Space Exploration
techniques for pragma insertion have significantly improved the Quality of Results of …
techniques for pragma insertion have significantly improved the Quality of Results of …
Lightning Talk: The Next Wave of High-level Synthesis
D Chen - 2023 60th ACM/IEEE Design Automation Conference …, 2023 - ieeexplore.ieee.org
Recent works established new High-Level Synthesis (HLS) solutions translating AI models
described in PyTorch to customized AI accelerators automatically. By adopting PyTorch as …
described in PyTorch to customized AI accelerators automatically. By adopting PyTorch as …
REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs
FPGA design optimization is challenging for developers for two main reasons. First,
developers cannot easily identify a bottleneck of the design to know where to focus …
developers cannot easily identify a bottleneck of the design to know where to focus …
FlexWalker: An Efficient Multi-Objective Design Space Exploration Framework for HLS Design
The HLS toolchain effectively reduces the design complexity of FPGA hardware
accelerators. However, in scenarios involving the multi-objective optimization of large-scale …
accelerators. However, in scenarios involving the multi-objective optimization of large-scale …
DeepFlexiHLS: Deep Neural Network Flexible High-Level Synthesis Directive Generator
M Riazati, M Daneshtalab, M Sjödin… - 2022 IEEE Nordic …, 2022 - ieeexplore.ieee.org
Deep Neural Networks (DNNs) are now widely adopted to solve various problems ranging
from speech recognition to image classification. Since DNNs demand a large amount of …
from speech recognition to image classification. Since DNNs demand a large amount of …
[图书][B] DeepKit: A Multistage Exploration Framework for Hardware Implementation of Deep Learning
M Riazati - 2023 - search.proquest.com
Abstract Deep Neural Networks (DNNs) are widely adopted to solve different problems
ranging from speech recognition to image classification. DNNs demand a large amount of …
ranging from speech recognition to image classification. DNNs demand a large amount of …