We present an intuitive 3D interface for interactively editing and painting a polygonal mesh
using a force feedback device. An artist or a designer can use the system to create and …

Applications that are co-scheduled on a multi-core compete for shared resources, such as
cache capacity and memory bandwidth. The performance degradation resulting from this …

Static timing analysis has traditionally used the PERT method for identifying the critical path
of a circuit. The authors show in this paper that due to the influence of the transition time of a …

Static timing analysis (STA) for large-scale modern circuits requires extensive handling of
false paths, multi-cycle paths, and other types of path exceptions. Despite the linear nature …

As design complexity rapidly grows, a modem design contains more complex constraints
and has more clock domains. To these stringent timing requirements, a design is iteratively …

Static timing analysis (STA) with multiple clock domains and complicated exception
conditions is a complex practical problem that can dramatically increase compilation time …

2002-12-06 Assigned to CADENCE DESIGN SYSTEMS, INC. reassignment CADENCE
DESIGN SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT …

A well-known problem in timing verification of VLSI circuits using static timing analysis tools
is the generation of false timing paths. This leads to a pessimistic estimation of the processor …

A combinational logic circuit may be represented as a timing graph G=(V, E), where the
elements of V, the vertex set, are the inputs and outputs of the logic gates in the circuit. e …

Modern FPGA chips contain multiple dedicated clocking networks, because nearly all real
designs contain multiple clock domains. In this paper, we present an FPGA technology …