Device structure for a 3-dimensional NOR memory array and methods for improved erase operations applied thereto

E Harari, RA Cernea, G Samachisa… - US Patent …, 2021 - Google Patents
(57) ABSTRACT A thin-film storage transistor includes (a) first and second polysilicon layers
of a first conductivity serving, respec tively, as a source terminal and a drain terminal of the …

Implementing logic function and generating analog signals using NOR memory strings

S Salahuddin, RD Normal, E Harari - US Patent 11,120,884, 2021 - Google Patents
NOR memory strings may be used for implementations of logic functions involving many
Boolean variables, or to generate analog signals whose magnitudes are each …

Integrated assemblies having ferroelectric transistors with body regions coupled to carrier reservoirs

KM Karda, H Liu - US Patent 10,748,931, 2020 - Google Patents
Some embodiments include an integrated assembly having a ferroelectric transistor body
region between a first comparative digit line and a second comparative digit line. A carrier …

Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages

KM Karda, C Mouli, S Pulugurtha… - US Patent 10,607,988, 2020 - Google Patents
Some embodiments include a memory cell with two tran sistors and one capacitor. The
transistors are a first transistor and a second transistor. The capacitor has a first node …

Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages

KM Karda, C Mouli, S Pulugurtha… - US Patent 10,381,357, 2019 - Google Patents
Some embodiments include a memory cell with two tran sistors and one capacitor. The
transistors are a first transistor and a second transistor. The capacitor has a first node …

Apparatuses having a vertical memory cell

KM Karda, RN Gupta, S Pulugurtha, CV Mouli… - US Patent …, 2017 - Google Patents
BACKGROUND The use of an access device with a storage element in memory cells is well
known in the art. Examples of memory devices that utilize access devices include dynamic …

High capacity memory circuit with low effective latency

YC Kim, RS Chernicoff, KN Quader… - US Patent …, 2023 - Google Patents
(57) ABSTRACT A first circuit formed on a first semiconductor substrate is wafer-bonded to a
second circuit formed on a second memory circuit, wherein the first circuit includes …

Apparatuses having body connection lines coupled with access devices

DC Pandey, H Liu, C Mouli, SD Tang - US Patent 10,269,805, 2019 - Google Patents
Some embodiments include an apparatus having a transistor associated with a vertically-
extending semiconductor pillar. The transistor includes an upper source/drain region within …

Channel controller for shared memory access

RD Norman, RS Chernicoff, E Harari - US Patent 11,561,911, 2023 - Google Patents
(57) ABSTRACT A shared memory provides multi-channel access from multiple computing
or host devices. A priority circuit prioritizes the multiple memory requests that are submitted …

Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies

KM Karda, H Liu, DVN Ramaswamy, Y Gao… - US Patent …, 2022 - Google Patents
Some embodiments include an integrated assembly having a carrier-sink-structure, and
having digit lines over the carrier-sink-structure. Transistor body regions are over the digit …