Much of the complexity and overhead (directory, state bits, invalidations) of a typical
directory coherence implementation stems from the effort to make it" invisible" even to the …

Large-scale CMPs with hundreds of cores require a directory-based protocol to maintain
cache coherence. However, previously proposed coherence directories are hard to scale …

Graphics processor units (GPUs) are designed to efficiently exploit thread level parallelism
(TLP), multiplexing execution of 1000s of concurrent threads on a relatively smaller set of …

Abstract System and methods for cache coherence in a multi-core processing environment
having a local/shared cache hierarchy. The system includes multiple processor cores, a …

Traditional directory coherence protocols are designed for the strictest consistency model,
sequential consistency (SC). When they are used for chip multiprocessors (CMPs) that …

Designing massive scale cache coherence systems has been an elusive goal. Whether it be
on large-scale GPUs, future thousand-core chips, or across million-core warehouse scale …

Programming for parallel architectures that do not have a shared address space is extremely
difficult due to the need for explicit communication between memories of different compute …

Conventional directory coherence operates at the finest granularity possible, that of a cache
block. While simple, this organization fails to exploit frequent application behavior: at any …

One of the key scalability challenges of on-chip coherence in a multicore chip is the
coherence directory, which provides information on sharing of cache blocks. Shadow tags …

Timing side channels have been used to extract cryptographic keys and sensitive
documents even from trusted enclaves. Specifically, cache side channels created by reuse …