Self-calibrated phase tuning system
L Wang, Y Song - US Patent 12,088,303, 2024 - Google Patents
A clock generation apparatus has a delay circuit, a phase selection circuit, and a phase
measurement circuit. The delay circuit outputs a first signal that is a delayed version of an …
measurement circuit. The delay circuit outputs a first signal that is a delayed version of an …
Methods and apparatus for providing a serializer and deserializer (serdes) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA)
GT Jennings - US Patent 11,874,792, 2024 - Google Patents
A method for providing a high-speed data communication between a host and field-
programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable …
programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable …
Quadrature circuit interconnect architecture with clock forwarding
M Sperling, DM Dreps, E English, J Qi - US Patent 11,979,480, 2024 - Google Patents
An integrated circuit communication architecture is provided and includes a clock lane, a
clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal …
clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal …
Methods and apparatus for providing a high-speed universal serial bus (USB) interface for a field-programmable gate array (FPGA)
GT Jennings - US Patent 11,843,376, 2023 - Google Patents
A system containing a host and a device having a field-programmable gate array (“FPGA”) is
disclosed. The system includes a set of configurable logic blocks (“LBs”), a bus, and a …
disclosed. The system includes a set of configurable logic blocks (“LBs”), a bus, and a …
Methods and apparatus for providing a serializer and deserializer (SERDES) block facilitating high-speed data transmissions for a field-programmable gate array …
GT Jennings - US Patent 11,474,969, 2022 - Google Patents
A method for providing a high-speed data communication between a host and field-
programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable …
programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable …