A higher level shared cache of a hierarchical cache of a multi-processor system utilizes
transaction identifiers to manage memory conflicts in corresponding transactions. The higher …

Throttling execution in a transaction operating in a processor configured to execute memory
instructions out-of-program-order in a pipelined processor, wherein memory instructions are …

2014-06-27 Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION
reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF …

Throttling instruction execution in a transaction operating in a processor configured to
execute memory instructions out-of-order in a pipelined processor, wherein memory …

(57) ABSTRACT A higher level shared cache of a hierarchical cache of a multi-processor
system utilizes transaction identifiers to manage memory conflicts in corresponding …

Improving the tracking of read sets and write sets associated with cache lines of a
transaction in a pipelined processor executing memory instructions having the read sets and …

US9864690B2 - Detecting cache conflicts by utilizing logical address comparisons in a
transactional memory - Google Patents US9864690B2 - Detecting cache conflicts by utilizing …

Managing cache evictions during transactional execution of a process. Based on initiating
transactional execution of a memory data accessing instruction, memory data is fetched from …

Determining, by a processor having a cache, if data in the cache is to be monitored for cache
coherency conflicts in a transactional memory (TM) environment. A processor executes a TM …

(57) ABSTRACT A computer allows non-cacheable loads or stores in a hardware
transactional memory environment. Transactional loads or stores, by a processor, are …