Graph-based term weighting for text categorization

FD Malliaros, K Skianis - Proceedings of the 2015 IEEE/ACM …, 2015 - dl.acm.org
Text categorization is an important task with plenty of applications, ranging from sentiment
analysis to automated news classification. In this paper, we introduce a novel graph-based …

Address sequences

VN Yarmolik, SV Yarmolik - Automatic Control and Computer Sciences, 2014 - Springer
A problem of generating modified address sequences is considered. The use of the
Euclidean distance as a disparity measure for address sequences is substantiated …

A reconfigurable INC/DEC/2's complement/priority encoder circuit with improved decision block

VC Kumar, PS Phaneendra, SE Ahmed… - … on electronic system …, 2011 - ieeexplore.ieee.org
An Increment/Decrement circuit is a common building block in many digital systems like
address generation unit which are used in micro controllers and microprocessors. Similarly …

A Scalable High-Speed Priority Encoder Design for Packet Classification

M Dhayalakumar, SK Mahammad - International Conference on Advanced …, 2024 - Springer
Abstract Ternary Content Addressable Memories (TCAMs) are used in modern routers to
perform packet classification at wire speed. Commercially available TCAMs come with built …

Address counter/generators for low power memory BIST

B Singh, SB Narang, A Khosla - International Journal of …, 2011 - search.proquest.com
Abstract In today's Integrated Circuits (IC's) designs Built-in Self Test (BIST) is becoming
important for the memory which is the most necessary part of the System on Chip. The March …

Testing of Neighborhood Pattern-Sensitive Faults for Memory

KLV Ramana Kumari, M Asha Rani, N Balaji - Soft Computing and Signal …, 2022 - Springer
The important fundamental integrated circuits (ICs) in system ICs and electronic systems are
semiconductor memories. With the increase in technology, the density, capacity of memory …

A Novel High Performance Universal Measurement Logic Element

S Murugesan, M Dhayalakumar… - 2020 IEEE 4th …, 2020 - ieeexplore.ieee.org
This paper proposes a novel universal measurement logic element. The proposed logic
element can be used as counter for increment and decrement of operations, the same logic …

[PDF][PDF] Design of efficient VLSI arithmetic circuits

S Veeramachaneni - … [Online] Available: https://shodhganga. inflibnet. ac …, 2015 - cdn.iiit.ac.in
Abstract Arithmetic and Logic Unit (ALU) is a critical component of any CPU. In ALU, adders
play a major role not only in addition but also in performing many other basic arithmetic …

[PDF][PDF] Design of a dynamic CMOS incrementer/decrementer and a parallel cascading architecture

B Archanadevi, V Anbumani, T Malathy… - … on Electronics and …, 2013 - researchgate.net
Dynamic CMOS based transistor level designs of incrementer/decrementer circuit is
presented in this work. The design of a new 8-bit decision module is first described. This is …

Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer

N Kaswan, I Munje, Y Kothari, P Gupta… - 2013 International …, 2013 - ieeexplore.ieee.org
The paper presents the implementation of a high speed energy efficient 4-bit binary CLA
based incrementer decrementer. The design methodology is extensively based on static …