Three dimensional circuit implementing machine trained network
SL Teig, K Duong - US Patent 11,176,450, 2021 - Google Patents
Some embodiments provide a three-dimensional (3D) cir cuit structure that has two or more
vertically stacked bonded layers with a machine-trained network on at least one bonded …
vertically stacked bonded layers with a machine-trained network on at least one bonded …
3D Compute circuit with high density z-axis interconnects
SL Teig, I Mohammed, K Duong, J Delacruz - US Patent 10,672,743, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In …
by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In …
3D compute circuit with high density Z-axis interconnects
SL Teig, I Mohammed, K Duong, J Delacruz - US Patent 10,672,744, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In …
by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In …
3D processor
SL Teig, I Mohammed, K Duong, J Delacruz - US Patent 10,672,745, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In …
by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In …
3D chip sharing power interconnect layer
J Delacruz, SL Teig, I Mohammed - US Patent 10,600,691, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
Self repairing neural network
SL Teig, K Duong - US Patent 10,762,420, 2020 - Google Patents
Some embodiments of the invention provide an integrated circuit (IC) with a defect-tolerant
neural network. The neural network has one or more redundant neurons in some …
neural network. The neural network has one or more redundant neurons in some …
3D chip sharing power circuit
J Delacruz, SL Teig, I Mohammed… - US Patent 10,672,663, 2020 - Google Patents
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
3D chip sharing data bus circuit
J Delacruz, SL Teig, I Mohammed - US Patent 10,600,780, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
3D chip sharing clock interconnect layer
J Delacruz, SL Teig, I Mohammed… - US Patent 10,586,786, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
Three dimensional chip structure implementing machine trained network
SL Teig, K Duong, J Delacruz - US Patent 10,719,762, 2020 - Google Patents
Some embodiments provide a three-dimensional (3D) cir cuit structure that has two or more
vertically stacked bonded layers with a machine-trained network on at least one bonded …
vertically stacked bonded layers with a machine-trained network on at least one bonded …