Computer memory comprises temporarily or permanently stored data and instructions, which
are utilized in electronic digital computers. The opposite of serial access memory is Random …

This paper presents the implementation of single-bit SRAM cell architecture along with its
peripherals in standard gpdk 90nm technology library using Cadence tool. Different …

Address decoders are integral components of random access memories. In higher-
performance computing, the timing of address decoders is often critical, especially in …

Rapid increase in technology is showing a great perception in assessing the complexity of
design that can be integrated on a single chip dramatically. Minimum feature sizes, low …

With the advent of technology, a change from feature size to nanometer regime resulted in
the scaling of operating voltages and dimensions. Reducing them can greatly boost the …

The main aim of this paper is to design a low power and noise resistant SRAM using
Cadence (version 6.1. 5) simulation tool. Standard gpdk180 library (ie, 180nm technology …

Objectives: The objective is to find the optimum SNM of SRAM and then a BIST architecture
is designed and implemented to test the SRAM cells varying the voltage of the bit lines …

This SRAM cell is composed of combination of normal transistors and high voltage threshold
transistors (sleep transistors) and can store one bit of data. Moreover, the designed SRAM …

There is an ever increasing need for running various multimedia and computer based
applications on a variety of popular digital systems. These applications continue to become …

SRAM (Static Random-Access Memory) is a memory component and is used in various VLSI
chips due to its unique capability to retain data. This memory cell has become a subject of …