A low-power high-speed comparator for precise applications

A Khorami, M Sharifkhani - IEEE Transactions on Very Large …, 2018 - ieeexplore.ieee.org
A low-power comparator is presented. pMOS transistors are used at the input of the
preamplifier of the comparator as well as the latch stage. Both stages are controlled by a …

Design Approaches of Ultra-Low Power SAR ADC for Biomedical Systems—A Review

K Aneesh, G Manoj, S Shylu Sam - Journal of Circuits, Systems and …, 2022 - World Scientific
In recent years, implantable biomedical devices like cardiac pacemaker, defibrillators,
cochlear implants, visual prosthesis etc. have gained immense importance in the personal …

A dynamic power-efficient 4 GS/s CMOS comparator

MA Dehkordi, M Dousti, SM Mirsanei… - AEU-International Journal …, 2023 - Elsevier
This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator.
The advantages of the proposed circuit are low kickback noise and offset. Moreover, low …

Design and analysis of ultra high-speed low-power double tail dynamic comparator using charge sharing scheme

V Varshney, RK Nagaria - AEU-International Journal of Electronics and …, 2020 - Elsevier
In this paper, an ultra high speed dynamic comparator is presented. The PMOS pass
transistors are used in the latch and pre-amplifier stage of the comparator. At the …

Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load

AK Dubey, RK Nagaria - Microelectronics Journal, 2018 - Elsevier
A novel approach is proposed and discussed for designing CMOS double-tail dynamic
comparator using the bulk-driven method. The bulk-driven method proposed thus far for low …

A low-power dynamic comparator for low-offset applications

A Khorami, R Saeidi, M Sachdev, M Sharifkhani - Integration, 2019 - Elsevier
In this paper, a low-power method for double-tail comparators is introduced. Using the
proposed method, the power consumption of the pre-amplifier which is the dominant part is …

CNTFET based comparators: design, simulation and comparative analysis

S Jogad, MS Akhoon, SA Loan - Analog Integrated Circuits and Signal …, 2023 - Springer
In this work, we design and simulate carbon nanotube field effect transistor (CNTFET) based
open-loop and dynamic comparators and compared the performance with complementary …

Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage

AK Dubey, RK Nagaria - Analog Integrated Circuits and Signal Processing, 2019 - Springer
This paper presents a low voltage double-tail dynamic comparator (DTDC) for fast and
power-efficient data conversion. The amplification stage of the proposed DTDC is designed …

A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology

H Ghasemian, R Ghasemi, E Abiri, MR Salehi - Microelectronics Journal, 2019 - Elsevier
The demand for high-performance analog-to-digital converters is pushing toward the
utilization of small dynamic comparators with low power consumption, low offset voltage …

Energy-efficient DAC switching technique for single-ended SAR ADCs

B Jajodia, A Mahanta, SR Ahamed - AEU-International Journal of …, 2020 - Elsevier
A novel energy-efficient digital-to-analog converter (DAC) switching technique applicable to
single-ended successive approximation register (SAR) analog-to-digital converter (ADC) is …