Roll-forward and rollback recovery: Performance-reliability trade-off

DK Pradhan, NH Vaidya - Proceedings of IEEE 24th …, 1994 - ieeexplore.ieee.org
Performance and reliability achieved by a modular redundant system depend on the
recovery scheme used. Typically, gain in performance using comparable resources results …

Towards the formal verification of security properties of a network-on-chip router

J Sepulveda, D Aboul-Hassan, G Sigl… - 2018 IEEE 23rd …, 2018 - ieeexplore.ieee.org
Vulnerabilities and design flaws in Network-on-Chip (NoC) routers can be exploited in order
to spy, modify and constraint the sensitive communication inside the Multi-Processors …

Formal verification of circuit-switched Network on chip (NoC) architectures using SPIN

A Zaman, O Hasan - … Symposium on System-on-Chip (SoC), 2014 - ieeexplore.ieee.org
Simulation techniques cannot cope with the distributive and reactive nature of Network on
chip (NoC) architectures very well and thus compromise on the accuracy of the analysis …

Formal modeling of network-on-chip using CFSM and its application in detecting deadlock

S Das, C Karfa, S Biswas - IEEE Transactions on Very Large …, 2020 - ieeexplore.ieee.org
A formal modeling of a Network-on-Chip (NoC) using a communicating finite state machine
(CFSM) is presented in this article. We have automated the CFSM model generation for …

Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects

S Saponara, L Fanucci, M Coppola - Microprocessors and Microsystems, 2011 - Elsevier
The work presents a configurable network interface (NI) macrocell to be integrated in
Spidergon network-on-chip (NoC) infrastructures, and addresses the problem of its …

An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis

Z Zhang, W Serwe, J Wu, T Yoneda, H Zheng… - Science of Computer …, 2016 - Elsevier
A fault-tolerant routing algorithm in Network-on-Chip (NoC) architectures provides adaptivity
for on-chip communications. Adding fault-tolerance adaptivity to a routing algorithm …

SoC Protocol Implementation Verification Using Instruction-Level Abstraction Specifications

H Lu, Y Xing, A Gupta, S Malik - ACM Transactions on Design …, 2023 - dl.acm.org
In modern systems-on-chips, several hardware protocols are used for communication and
interaction among different modules. These protocols are complex and need to be …

Design and multi-abstraction-level evaluation of a noc router for mixed-criticality real-time systems

M Dridi, S Rubini, M Lallali, MJS Flórez… - ACM Journal on …, 2019 - dl.acm.org
A Mixed Criticality System (MCS) combines real-time software tasks with different criticality
levels. In a MCS, the criticality level specifies the level of assurance against system failure …

NoCFuzzer: Automating NoC Verification in UVM

R Ma, J Huang, S Zhang, Y Xie… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Network-on-Chip (NoC) has surfaced as a crucial interconnection strategy in modern digital
systems, thereby demanding meticulous verification. Due to its multiple nodes and high …

[PDF][PDF] Comparison of NoC routing algorithms using formal methods

Z Sharifi, S Mohammadi, M Sirjani - Proceedings of the International …, 2013 - world-comp.org
Network on Chip (NoC) has emerged as a promising interconnection paradigm for complex
on-chip communications. As fabrication cost is high, model based design of NoC and early …