A review on power supply induced jitter
JN Tripathi, VK Sharma… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
The primary focus of this paper is to discuss the modeling of jitter caused by power supply
noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented …
noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented …
[图书][B] Through silicon vias: materials, models, design, and performance
Recent advances in semiconductor technology offer vertical interconnect access (via) that
extend through silicon, popularly known as through silicon via (TSV). This book provides a …
extend through silicon, popularly known as through silicon via (TSV). This book provides a …
[图书][B] Model and design of bipolar and MOS current-mode logic: CML, ECL and SCL digital circuits
Current-Mode digital circuits have been extensively analyzed and used since the early days
of digital ICs. In particular, bipolar Current-Mode digital circuits emerged as an approach to …
of digital ICs. In particular, bipolar Current-Mode digital circuits emerged as an approach to …
Mixed full adder topologies for high-performance low-power arithmetic circuits
This paper deals with the implementation of Full Adder chains by mixing different CMOS Full
Adder topologies. The approach is based on cascading fast Transmission-Gate Full Adders …
Adder topologies. The approach is based on cascading fast Transmission-Gate Full Adders …
Low-jitter multi-output all-digital clock generator using DTC-based open loop fractional dividers
An all-digital reconfigurable multi-output clock generator is presented. A digital phase-
locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional …
locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional …
A new gate delay model for simultaneous switching and its applications
LC Chen, SK Gupta, MA Breuer - Proceedings of the 38th annual Design …, 2001 - dl.acm.org
We present a new model to capture the delay phenomena associ-ated with simultaneous to-
controlling transitions. The proposed delay model accurately captures the effect of the …
controlling transitions. The proposed delay model accurately captures the effect of the …
Transient analysis of CMOS-gate-driven $ RLGC $ interconnects based on FDTD
XC Li, JF Mao, M Swaminathan - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
As the feature size of integrated circuits shrinking in deep submicron technologies, time
delay, and crosstalk noise of complementary metal-oxide-semiconductor (CMOS)-gate …
delay, and crosstalk noise of complementary metal-oxide-semiconductor (CMOS)-gate …
Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies
Z Huang, A Kurokawa, M Hashimoto… - IEEE transactions on …, 2010 - ieeexplore.ieee.org
With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the
nanometer regime, the overshooting effect due to the input-to-output coupling capacitance …
nanometer regime, the overshooting effect due to the input-to-output coupling capacitance …
[图书][B] System-level design methodologies for telecommunication
System-level design methodologies for telecommunication Page 2 System-Level Design
Methodologies for Telecommunication Page 3 Nicolas Sklavos• Michael Hübner Diana …
Methodologies for Telecommunication Page 3 Nicolas Sklavos• Michael Hübner Diana …
An analytical model for current, delay, and power analysis of submicron CMOS logic circuits
AA Hamoui, NC Rumin - … on Circuits and Systems II: Analog …, 2000 - ieeexplore.ieee.org
An analytical model for computing the supply current, delay, and power of a submicron
CMOS inverter is presented. A modified version of the nth power law MOSFET model is …
CMOS inverter is presented. A modified version of the nth power law MOSFET model is …