The complexity of the chip is increasing as the advances in VLSI technology leads to the
accumulation of more and more devices on a single chip. Since the chip has high density …

This paper describes the design of high speed Vedic multiplier that uses the techniques of
Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this …

This paper briefly describes the Urdhva-Tiryagbhyam Sutra of vedic mathematics and we
have designed multiplier based on the sutra. Vedic Mathematics is the ancient system of …

The Vedic multiplication algorithm is a very fast way of oral calculation. However, the basis
of the algorithm is not available so far. The present paper demystifies the general Vedic …

Augmenting teaching with visualization can help students understand concepts better.
Researchers have leveraged visualization to teach conventional mathematics some …

An Ancient system of Indian mathematics is known as Vedic mathematics. It is a gift given to
this world by ancient stages of India. The Vedic mathematics was constructed using 16 …

Hardware efficient architectures are the next generation VLSI devices in the Internet of
Things. Internet of Things demands ubiquitous devices that collect and process the sensed …

In recent years, due to the rapid growth of high performance digital systems, speed and
power consumption become very vital in multiplier design. In this paper, a 4x4 bit Vedic …

This paper presents a model of a reversible Vedic multiplier using ancient Vedic
mathematical techniques. The composed Vedic multiplier used Urdhva Tiryakbhayam …

This paper presents a model of a reversible Vedic multiplier using ancient Vedic
mathematical techniques. The composed Vedic multiplier used Urdhva Tiryakbhayam …