Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling
Markov chain Monte Carlo (MCMC) is a widely used sampling method in modern artificial
intelligence and probabilistic computing systems. It involves repetitive random number …
intelligence and probabilistic computing systems. It involves repetitive random number …
PipeCIM: A High-Throughput Computing-In-Memory Microprocessor With Nested Pipeline and RISC-V Extended Instructions
T Chen, W Wang, J Chen, H Fu, W Yi… - … on Circuits and …, 2024 - ieeexplore.ieee.org
The large number of multiply accumulate (MAC) operations in Convolutional Neural Network
(CNN) leads to substantial data migration and computation. Although computing-in-memory …
(CNN) leads to substantial data migration and computation. Although computing-in-memory …
RDCIM: RISC-V Supported Full-Digital Computing-in-Memory Processor With High Energy Efficiency and Low Area Overhead
W Yi, K Mo, W Wang, Y Zhou, Y Zeng… - … on Circuits and …, 2024 - ieeexplore.ieee.org
Digital computing-in-memory (DCIM) that merges computing logic into memory has been
proven to be an efficient architecture for accelerating multiply-and-accumulates (MACs) …
proven to be an efficient architecture for accelerating multiply-and-accumulates (MACs) …
An End-to-End In Memory Computing System Based On A 40nm eFlash-Based IMC SoC: Circuits, Toolchains, and Systems Co-Design Framework
T Bai, W Mao, G Wang, H Liu, A Zhang… - … on Computer-Aided …, 2024 - ieeexplore.ieee.org
Despite its promising potential for artificial intelligence (AI) applications, current in-memory
computing (IMC) technology faces a variety of challenges before mass production. One of …
computing (IMC) technology faces a variety of challenges before mass production. One of …
An In-Memory-Computing STT-MRAM Macro with Analog ReLU and Pooling Layers for Ultra-High Efficient Neural Network
In-memory computing (IMC) technology has great potential for neural network accelerators.
However, the energy efficiency of current mainstream IMC designs is limited, since the …
However, the energy efficiency of current mainstream IMC designs is limited, since the …
A Hierarchically Reconfigurable SRAM-Based Compute-in-Memory Macro for Edge Computing
AI running on the edge requires silicon that can meet demanding performance requirements
while meeting the aggressive power and area budget. Frequently updated AI algorithms …
while meeting the aggressive power and area budget. Frequently updated AI algorithms …