On-chip delay measurement circuit
A Jain, A Veggetti, D Crippa… - 2012 17th IEEE …, 2012 - ieeexplore.ieee.org
A novel On-chip delay measurement circuit is presented which is suitable for wide
applications involving on-chip measurements, monitoring and process compensation. The …
applications involving on-chip measurements, monitoring and process compensation. The …
An on-chip flip-flop characterization circuit
A Jain, A Veggetti, D Crippa, P Rolandi - Integrated Circuit and System …, 2011 - Springer
The performance of the sequential digital circuit (Speed, Power consumption etc.) depends
upon the performance of flip-flop used in the design. ASIC design flows use characterized …
upon the performance of flip-flop used in the design. ASIC design flows use characterized …
[PDF][PDF] Standard Cell Library Validation Methodology
M De Carvalho, B Canal, L Puricelli… - Workshop Circuits and …, 2016 - researchgate.net
In digital IC design, the standard cell-based design is the most used in the industry. It
accounts on a mature validated cell library to quickly design a reliable commercial IC …
accounts on a mature validated cell library to quickly design a reliable commercial IC …
[PDF][PDF] COST-EFFICIENT STANDARD CELL LIBRARY TIMING AND POWER VALIDATION TECHNIQUES
JKK AL-FRAJAT - 2015 - psasir.upm.edu.my
This chapter introduces the present research and provides an overview of the design of
application-specific integrated circuits (ASIC), including the standard cell library, which forms …
application-specific integrated circuits (ASIC), including the standard cell library, which forms …
Area efficient test circuit for library standard cell qualification
JK Al-Frajat, WN Flayyih, RBM Sidek… - … on Energy Aware …, 2015 - ieeexplore.ieee.org
High cost of qualifying library standard cells on silicon wafer limits the number of test circuits
on the test chip. This paper proposes a technique to share common load circuits among test …
on the test chip. This paper proposes a technique to share common load circuits among test …