Language and compilation of parallel programs for*-predictable MPSoC execution using invasive computing

J Teich, M Glaß, S Roloff… - 2016 IEEE 10th …, 2016 - ieeexplore.ieee.org
The predictability of execution qualities including timeliness, power consumption, and fault-
tolerability is of utmost importance for the successful introduction of multi-core architectures …

SHARQ: Software-defined hardware-managed queues for tile-based manycore architectures

S Rheindt, S Maier, F Schmaus, T Wild… - … , and Simulation: 19th …, 2019 - Springer
The recent trend towards tile-based manycore architectures has helped to tackle the
memory wall by physically distributing memories and processing nodes. Distributed …

Pegasus: efficient data transfers for PGAS languages on non-cache-coherent many-cores

M Mohr, C Tradowsky - Design, Automation & Test in Europe …, 2017 - ieeexplore.ieee.org
To improve scalability, some many-core architectures abandon global cache coherence, but
still provide a shared address space. Partitioning the shared memory and communicating …

CAP: Communication aware programming

J Heisswolf, A Zaib, A Zwinkau, S Kobbe… - Proceedings of the 51st …, 2014 - dl.acm.org
Networks on Chip (NoC) come along with increased complexity from the implementation
and management perspective. This leads to higher energy consumption and programming …

A framework for multi-fpga interconnection using multi gigabit transceivers

M Dreschmann, J Heisswolf, M Geiger… - Proceedings of the 28th …, 2015 - dl.acm.org
In this paper we present an interconnect framework for FPGAs based on multi gigabit
transceivers (MGTs), typically available in modern reconfigurable devices. The framework …

Fault-tolerant communication in invasive networks on chip

J Heisswolf, A Weichslgartner, A Zaib… - 2015 NASA/ESA …, 2015 - ieeexplore.ieee.org
Dependability and fault tolerance will play an ever increasing role when using future
technology nodes. The paper presents a fault-tolerance strategy for invasive networks on …

Hardware/software debugging of large scale many-core architectures

S Friederich, J Heisswolf, J Becker - Proceedings of the 27th …, 2014 - dl.acm.org
The size of current multi-processor system-on-chip (MPSoC) is growing unsustainable.
Besides, new decentralized software approaches are being developed to handle the …

A square-root sampling approach to fast histogram-based search

HW Chang, HT Chen - 2010 IEEE Computer Society …, 2010 - ieeexplore.ieee.org
We present an efficient pixel-sampling technique for histogram-based search. Given a
template image as a query, a typical histogram-based algorithm aims to find the location of …

DySHARQ: dynamic software-defined hardware-managed queues for tile-based architectures

S Rheindt, S Maier, N Pohle, L Nolte, O Lenke… - International Journal of …, 2021 - Springer
The recent trend towards tile-based manycore architectures has helped to tackle the
memory wall by physically distributing memories and processing nodes. However, this …

Providing fault tolerance through invasive computing

V Lari, A Weichslgartner, A Tanase… - it-Information …, 2016 - degruyter.com
As a consequence of technology scaling, today's complex multi-processor systems have
become more and more susceptible to errors. In order to satisfy reliability requirements, such …