Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer

JC Costa - US Patent 9,812,350, 2017 - Google Patents
(57) ABSTRACT A semiconductor device and methods for manufacturing the same are
disclosed. The semiconductor device includes a polymer substrate and an interfacial layer …

Flip chip module with enhanced properties

JC Costa, TS Morris, JH Hammond… - US Patent …, 2018 - Google Patents
A flip chip module having at least one flip chip die is disclosed. The flip chip module includes
a carrier having a top surface with a first mold compound residing on the top surface. A first …

Method for manufacturing an integrated circuit package

JC Costa, G Maxim, DRW Leipold, B Scott - US Patent 10,085,352, 2018 - Google Patents
This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the
same. In one method, a printed circuit board is provided with semiconductor die. The …

Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same

DRW Leipold, JC Costa, B Scott - US Patent 9,824,951, 2017 - Google Patents
A printed circuit module and methods for manufacturing the same are disclosed. The printed
circuit module includes a printed circuit substrate with a thinned die attached to the printed …

Silicon-on-plastic semiconductor device with interfacial adhesion layer

JC Costa - US Patent 10,134,627, 2018 - Google Patents
(57) ABSTRACT A semiconductor device and methods for manufacturing the same are
disclosed. The semiconductor device includes a polymer substrate and an interfacial layer …

Wafer-level package with enhanced performance

MA Hatcher, JH Hammond, J Chadwick… - US Patent …, 2019 - Google Patents
The present disclosure relates to a wafer-level package that includes a first thinned die, a
multilayer redistribution structure, a first mold compound, and a second mold compound …

Method of manufacture for a semiconductor device

JC Costa, DM Shuttleworth, MJ Antonell - US Patent 10,062,637, 2018 - Google Patents
A method of manufacture for a semiconductor device is disclosed. The method includes
providing a semiconductor stack structure that includes a device terminal of a semiconductor …

Wafer-level package with enhanced performance

JC Costa, J Chadwick, D Jandzinski… - US Patent …, 2020 - Google Patents
The present disclosure relates to a wafer-level package that includes a first thinned die
having a first device layer, a multilayer redistribution structure, a first mold compound, and a …

Thermally enhanced semiconductor package with thermal additive and process for making the same

JC Costa, G Maxim, DRW Leipold, B Scott… - US Patent …, 2018 - Google Patents
The present disclosure relates to a thermally enhanced semiconductor package, which
includes a module substrate, a thinned flip chip die over the substrate, a first mold …

Wafer-level package with enhanced performance

JC Costa, JH Hammond, JE Vandemeer… - US Patent …, 2018 - Google Patents
The present disclosure relates to a packaging process to enhance thermal and electrical
performance of a wafer-level package. The wafer-level package with enhanced performance …