Next-generation delta-sigma converters: Trends and perspectives
JM de la Rosa, R Schreier, KP Pun… - IEEE Journal on …, 2015 - ieeexplore.ieee.org
This paper presents an overview of emerging circuits and systems techniques which are at
the forefront of the state of the art in ΔΣ modulators, pushing their performance forward and …
the forefront of the state of the art in ΔΣ modulators, pushing their performance forward and …
Review of analog-to-digital conversion characteristics and design considerations for the creation of power-efficient hybrid data converters
SA Zahrai, M Onabajo - Journal of Low Power Electronics and …, 2018 - mdpi.com
This article reviews design challenges for low-power CMOS high-speed analog-to-digital
converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding …
converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding …
[图书][B] CMOS sigma-delta converters: Practical design guide
JM De la Rosa, R Del Rio - 2013 - books.google.com
A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a
practical guide to their design in nano-scale CMOS for optimal performance. This book …
practical guide to their design in nano-scale CMOS for optimal performance. This book …
An 8.5 mW Continuous-Time Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR
This paper presents a third order, single-loop, continuous-time ΔΣ modulator with an internal
4-bit quantizer. The modulator is sampled at 500 MHz, and features an oversampling ratio of …
4-bit quantizer. The modulator is sampled at 500 MHz, and features an oversampling ratio of …
A 43-mW MASH 2-2 CT Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS
This paper proposes a multistage noise-shaping continuous-time sigma-delta modulator
(CTΣΔM) with on-chip RC time constant calibration circuits, multiple feedforward interstage …
(CTΣΔM) with on-chip RC time constant calibration circuits, multiple feedforward interstage …
[图书][B] CMOS time-mode circuits and systems: fundamentals and applications
F Yuan - 2018 - books.google.com
Time-mode circuits, where information is represented by time difference between digital
events, offer a viable and technology-friendly means to realize mixed-mode circuits and …
events, offer a viable and technology-friendly means to realize mixed-mode circuits and …
AI-assisted sigma-delta converters—Application to cognitive radio
JM de la Rosa - IEEE Transactions on Circuits and Systems II …, 2022 - ieeexplore.ieee.org
This brief discusses the use of Artificial Intelligence (AI) to manage the operation and
improve the performance of Analog-to-Digital Converters (ADCs) based on Sigma-Delta …
improve the performance of Analog-to-Digital Converters (ADCs) based on Sigma-Delta …
AI-managed cognitive radio digitizers
JM de la Rosa - IEEE Circuits and Systems Magazine, 2022 - ieeexplore.ieee.org
Embedding Artificial Intelligence (AI) in integrated circuits is one of the technology pillars of
the so-called digital transformation. Nowadays, the vast majority of electronic devices …
the so-called digital transformation. Nowadays, the vast majority of electronic devices …
A 16 MHz BW 75 dB DR CT ADC Compensated for More Than One Cycle Excess Loop Delay
The maximum sampling rate of a continuous-time ΔΣ modulator in a given process is limited
by the minimum flash ADC delay that can be realized. Excess loop delay compensation …
by the minimum flash ADC delay that can be realized. Excess loop delay compensation …
A 15-MHz Bandwidth 1-0 MASH ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR
SC Lee, Y Chiu - IEEE Journal of Solid-State Circuits, 2014 - ieeexplore.ieee.org
A 1-0 MASH ΣΔ analog-to-digital converter (ADC) demonstrates a digital linearization
technique for the first time treating integrator distortion with memory and capacitor mismatch …
technique for the first time treating integrator distortion with memory and capacitor mismatch …