Hypersentry: enabling stealthy in-context measurement of hypervisor integrity

AM Azab, P Ning, Z Wang, X Jiang, X Zhang… - Proceedings of the 17th …, 2010 - dl.acm.org
This paper presents HyperSentry, a novel framework to enable integrity measurement of a
running hypervisor (or any other highest privileged software layer on a system). Unlike …

Hypercheck: A hardware-assistedintegrity monitor

F Zhang, J Wang, K Sun… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
The advent of cloud computing and inexpensive multi-core desktop architectures has led to
the widespread adoption of virtualization technologies. Furthermore, security researchers …

A Survey of Hardware Improvements to Secure Program Execution

L Zhao, H Shuang, S Xu, W Huang, R Cui… - ACM Computing …, 2024 - dl.acm.org
Hardware has been constantly augmented for security considerations since the advent of
computers. There is also a common perception among computer users that hardware does a …

Synthesizing near-optimal malware specifications from suspicious behaviors

M Fredrikson, S Jha, M Christodorescu… - … IEEE Symposium on …, 2010 - ieeexplore.ieee.org
Fueled by an emerging underground economy, malware authors are exploiting
vulnerabilities at an alarming rate. To make matters worse, obfuscation tools are commonly …

Hardware security in practice: Challenges and opportunities

N Potlapally - 2011 IEEE International Symposium on Hardware …, 2011 - ieeexplore.ieee.org
Computing platforms used in practice are complex and require interaction between multiple
hardware components (such as processor, chipset, memory and peripherals) for their …

Sice: a hardware-level strongly isolated computing environment for x86 multi-core platforms

AM Azab, P Ning, X Zhang - Proceedings of the 18th ACM conference on …, 2011 - dl.acm.org
SICE is a novel framework to provide hardware-level isolation and protection for sensitive
workloads running on x86 platforms in compute clouds. Unlike existing isolation techniques …

Cache storage channels: Alias-driven attacks and verified countermeasures

R Guanciale, H Nemati, C Baumann… - 2016 IEEE Symposium …, 2016 - ieeexplore.ieee.org
Caches pose a significant challenge to formal proofs of security for code executing on
application processors, as the cache access pattern of security-critical services may leak …

Using hardware features for increased debugging transparency

F Zhang, K Leach, A Stavrou, H Wang… - 2015 IEEE Symposium …, 2015 - ieeexplore.ieee.org
With the rapid proliferation of malware attacks on the Internet, understanding these
malicious behaviors plays a critical role in crafting effective defense. Advanced malware …

[PDF][PDF] Attacking SMM memory via Intel CPU cache poisoning

R Wojtczuk, J Rutkowska - Invisible Things Lab, 2009 - Citeseer
SMM Cache Fun - final Page 1 Attacking SMM Memory via Intel® CPU Cache Poisoning Rafal
Wojtczuk Joanna Rutkowska rafal@invisiblethingslab.com joanna@invisiblethingslab.com …

SoK: A study of using hardware-assisted isolated execution environments for security

F Zhang, H Zhang - Proceedings of the Hardware and Architectural …, 2016 - dl.acm.org
Hardware-assisted Isolated Execution Environments (HIEEs) have been widely adopted to
build effective and efficient defensive tools for securing systems. Hardware vendors have …