A new design of a low-power reversible Vedic multiplier

M Rashno, M Haghparast, M Mosleh - International Journal of …, 2020 - World Scientific
In recent years, there has been an increasing tendency towards designing circuits based on
reversible logic, and has received much attention because of preventing internal power …

Low Power High Speed Vedic Techniques in Recent VLSI Design–A Survey

S Dayanand, KR Varshitha, T Rohini… - … -systems and Signal …, 2020 - pices-journal.com
Abstract Advancement in the Artificial Intelligence (AI) and Machine Learning (ML) has
influenced complex designs to be integrated in Very Large-Scale Integration (VLSI) Design …

[PDF][PDF] Design of Complex Multiplier Using Vedic Mathematics

H Hassan - International Journal of Integrated Engineering, 2023 - publisher.uthm.edu.my
In this project, a 4x4 multiplier is implemented that utilizes the Urdhava Tiryakbhyam sutra
method in Vedic mathematics. This method is applicable in all two decimal number …

[PDF][PDF] HDL implementation and performance comparison of an optimized high speed multiplier

A Sahu, SK Panda, SP Jena - International Organization Of Scientific …, 2015 - academia.edu
This paper is devoted for the design of an optimized high speed Vedic multiplier using
Udhava-Tiryakbhyam sutra. High speed multiplier is required to perform critical …

[HTML][HTML] High-Performance FIR Filter Implementation Using Anurupye Vedic Multiplier

S Jayakumar, A Sumathi - Circuits and Systems, 2016 - scirp.org
In this, today's world immeasurable analysis goes within the field of communication and
signal processing applications. The FIR filter is mostly employed in filtering applications to …

[PDF][PDF] Design of high speed 64x64 bit fault tolerant reversible Vedic multiplier

A Sahu, AK Sahu - … Reseach Journal of Engineering and Technology, 2015 - academia.edu
Multiplier is the most widely used arithmetic unit, having great importance in the digital
world. For example-Digital Signal Processing, Processor and Quantum Computing etc. The …

Design and implementation of multipliers

P Gaharwar, A Johari - 2016 IEEE Students' Conference on …, 2016 - ieeexplore.ieee.org
In this paper the design of multipliers which is less complex and power consuming is made
of basic electronic components such as gates and adders. This design lowers the complexity …