Digit-Size Selection for FPGA Implementation of Generic Digit-Serial Multiplication Over GF (2m)

Input–output scheduling and control for efficient FPGA realization of digit-serial multiplication over generic binary extension fields

D Pradhan, PK Meher, BK Meher - Circuits, Systems, and Signal …, 2024 - Springer
In this paper, we propose an energy-efficient design of architecture for digit-serial
multiplication over generic GF (2 m), which could be used for different fields as and when …
被引用次数：1 相关文章 所有 3 个版本

FPGA-Specific Efficient Designs of Digit-Serial Multiplier for Galois Field GF

D Pradhan, PK Meher, BK Meher - Circuits, Systems, and Signal …, 2024 - Springer
FPGA-specific efficient LUT-based designs for the digit-serial multiplication over GF (2 m)
are presented. It is shown that composite logic could be mapped to LUTs directly using the …
相关文章 所有 2 个版本