Digital ASIC Implementation of RISC-V: OpenLane and Commercial Approaches in Comparison

S Hesham, M Shalan, MW El-Kharashi… - … on Circuits and …, 2021 - ieeexplore.ieee.org
Computer Aided Design (CAD) tools are widely used in Application Specific Integrated
Circuit (ASIC) design. CAD tools provide a simple process for the IC design. For that …

Lightweight ASIP Design for Lattice-Based Post-quantum Cryptography Algorithms

L Akçay, BÖ Yalçın - Arabian Journal for Science and Engineering, 2024 - Springer
Lattice-based cryptography (LBC) algorithms are considered suitable candidates for post-
quantum cryptography (PQC), as they dominate the standardization process put forward by …

[PDF][PDF] ISTANBUL TECHNICAL UNIVERSITY 击GRADUATE SCHOOL

L AKÇAY - 2022 - polen.itu.edu.tr
The study is introduced under four main sections in this chapter. First, the purpose of the
thesis is explained clearly. Afterwards, a detailed literature review is given in order to …

Hardware Design and Verification with Large Language Models: A Scoping Review, Challenges, and Open Issues

M Abdollahi, SF Yeganli, MA Baharloo, A Baniasadi - Electronics, 2025 - mdpi.com
Background: Large Language Models (LLMs) are emerging as promising tools in hardware
design and verification, with recent advancements suggesting they could fundamentally …

SUTRA: Methodology and Sign-off

R Nandika, M Varsha… - 2023 14th International …, 2023 - ieeexplore.ieee.org
VLSI technology is specifically tailored to meet the requirements of contemporary electronic
devices and systems. Although the ASIC (Application-Specific Integrated Circuit) flow …

[PDF][PDF] Hardware Design and Verification with Large Language Models: A Literature Survey, Challenges, and Open Issues

M Abdollahi, SF Yeganli, MA Baharloo, A Baniasadi - 2024 - preprints.org
Large Language Models (LLMs) are emerging as promising tools in hardware design and
verification, with recent advancements suggesting they could fundamentally reshape …

Implementation of a 32-bit MAC unit in AISC flow using Vedic Multiplier and CSA

AA Bharadwaj, K Manu, D Upadhya… - … on Intelligent and …, 2024 - ieeexplore.ieee.org
This paper majorly focuses on the developing an IP ie, a 32-bit MAC in Verilog HDL using
Vedic multiplier along with CSA and implementation of design using ASIC flow. This is a …

Slack Time Analysis for APB Timer Using Genus Synthesis Tool

R Madhura, KH Krishnappa, R Manasa… - … Conference on ICT for …, 2023 - Springer
Synthesis plays an important role in the complex world of chip design, as constant push to
improve chip—to get more performance, lower power, and improved area. In an effort to …