Pre-charging two or more sets of nodes to set a differential output of a multi-input summation
latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets …

Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS)
clock and data recovery circuits having configurable sub-channel multi-input comparator …

Methods and systems are described for generating two comparator outputs by comparing a
received signal to a first threshold and a second threshold according to a sampling clock, the …

Generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local
oscillator signal, generating a loop error signal based on a comparison of one or more …

In an example, an apparatus for clock data recovery (CDR) in a receiver includes a decision
feedback equalizer (DFE) having a data slicer providing data samples, an error slicer …

A decision-feedback equalizer for use in a receiver unit for receiving an incoming data
stream and for providing a stream of bit data outputs includes a plurality of asynchronous …

Methods and systems are described for generating, at a plurality of delay stages of a local
oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal …

Methods and systems are described for receiving a plurality of signals in a signaling interval
at a multi-input comparator (MIC), and responsively generating an analog linear …

6462.584 B1 10/2002 Proebsting 2 ()() 7/() 1 88367 A 1 8/2 ()() 7 Yamada 6,563.382 B1
5/2003 Yang 2 ()() 7/() 2 () 1 546 A1 8/2 ()() 7 I ee 66 24.699 B2 9/2003 Yin et al. 2 ()() …

375/232 (Continued) Primary Examiner—James M Perez (74) Attorney, Agent, or Firm—
Robert M. Brush (57) ABSTRACT An example method of performing an eye-scan in a …