Petri net dynamic partial reconfiguration in FPGA
A Bukowiec, M Doligalski - … Aided Systems Theory-EUROCAST 2013: 14th …, 2013 - Springer
The rigorous digital design of embedded Application Specific Logic Controllers starts from
algorithm designed with concurrent hierarchical control interpreted Petri net and then …
algorithm designed with concurrent hierarchical control interpreted Petri net and then …
Synthesis of Petri nets into FPGA with operation flexible memories
A Bukowiec, M Adamski - 2012 IEEE 15th International …, 2012 - ieeexplore.ieee.org
In this paper a new method of Petri net array-based synthesis is proposed. The method is
based on the structured encoding of places by means of using minimal numbers of bits …
based on the structured encoding of places by means of using minimal numbers of bits …
Logic design of structured configurable controllers
The paper is concentrated on behavioral and structural specification of reconfigurable logic
controllers (RLC). The initial description is given as a hierarchical modular control …
controllers (RLC). The initial description is given as a hierarchical modular control …
[PDF][PDF] Implementation of algorithm of Petri nets distributed synthesis into FPGA
In the paper an implementation of algorithm of Petri net array-based synthesis is presented.
The method is based on decomposition of colored interpreted macro Petri net into subnets …
The method is based on decomposition of colored interpreted macro Petri net into subnets …
[PDF][PDF] Synthesis of macro Petri nets into FPGA with distributed memories
A Bukowiec, M Adamski - International Journal of Electronics and …, 2012 - bibliotekanauki.pl
In this paper a new method of Petri net array-based synthesis is proposed. The method is
based on decomposition of colored interpreted macro Petri net into state machine subnets …
based on decomposition of colored interpreted macro Petri net into state machine subnets …
Design of reconfigurable logic controllers from petri net-based specifications
The paper promotes to construct a synthesizable VHDL model from a graphical
representation of Petri Net. The VHDL code provides a clear semantics of graphically …
representation of Petri Net. The VHDL code provides a clear semantics of graphically …
Logic synthesis for FPGAs of interpreted Petri net with common operation memory
A Bukowiec, M Adamski - IFAC Proceedings Volumes, 2012 - Elsevier
The method of synthesis of the logic circuit of interpreted Petri net is proposed in this paper.
Proposed method is based on the minimal encoding of places. Places are encoded in …
Proposed method is based on the minimal encoding of places. Places are encoded in …
[PDF][PDF] Wyznaczanie SM-pokrycia bezpiecznej sieci Petriego metodą komputerowego wnioskowania
W artykule przedstawiono nowy sposób pokrywania bezpiecznej sieci Petriego minimalną
liczbą podsieci automatowych. Metoda symboliczna polega na wczesnej selekcji …
liczbą podsieci automatowych. Metoda symboliczna polega na wczesnej selekcji …
Hierarchical configurable Petri net modeling in VHDL
M Doligalski, M Adamski - International Journal of Electronics and …, 2012 - yadda.icm.edu.pl
The paper presents method for hierarchical configurable Petri nets description in VHDL
language. Dual model is an alternative way for behavioral description of the discrete control …
language. Dual model is an alternative way for behavioral description of the discrete control …
Modelling of Concurrent Systems in Hardware Languages
R Wiśniewski, R Wiśniewski - Prototyping of Concurrent Control Systems …, 2017 - Springer
The modelling techniques of the concurrent control systems in hardware description
languages (HDLs) are presented in this chapter. Two modelling approaches are shown. The …
languages (HDLs) are presented in this chapter. Two modelling approaches are shown. The …