Memory controller and method of data bus inversion using an error detection correction code

FA Ware, JE Linstadt - US Patent 9,979,416, 2018 - Google Patents
Memory controllers, devices and associated methods are disclosed. In one embodiment, a
memory controller includes write circuitry to transmit write data to a memory device, the write …

Apparatuses and methods for performing intra-module databus inversion operations

TM Hollis, HT Vo, D Khatri - US Patent 9,922,686, 2018 - Google Patents
Apparatuses, memory modules, and methods for performing intra-module data bus inversion
operations are described. An example apparatus include a memory module comprising a …

Apparatuses and methods for performing a databus inversion operation

S Ayyapureddi, D Morgan, MG Won - US Patent 9,405,721, 2016 - Google Patents
Advances in technology have resulted in making electronic devices Smaller and faster,
while consuming less power. In an effort to reduce power consumption while communicating …

Semiconductor layered device with data bus

C Kondo, A Funahashi - US Patent 10,146,719, 2018 - Google Patents
Apparatuses and methods of data communication between semiconductor chips are
described. An example apparatus includes: a first die including a first switch circuit that …

Apparatuses and methods for performing intra-module databus inversion operations

TM Hollis, HT Vo, D Khatri - US Patent 10,297,294, 2019 - Google Patents
Apparatuses, memory modules, and methods for performing intra-module data bus inversion
operations are described. An example apparatus include a memory module comprising a …

Signaling mechanism for bus inversion

SD Hanna, JS Parry - US Patent 11,294,838, 2022 - Google Patents
Methods, systems, and devices that support signaling mechanisms for bus inversion are
described. A control signal that supports transferring information from a first controller to a …

Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories

Y Riho, A Shimizu, SK Park, J Kwak - US Patent 10,795,759, 2020 - Google Patents
Apparatuses and methods for error correction coding and data bus inversion for
semiconductor memories are described. An example apparatus includes an I/O circuit …

Semiconductor layered device with data bus

C Kondo, A Funahashi - US Patent 10,635,623, 2020 - Google Patents
Apparatuses and methods of data communication between semiconductor chips are
described. An example apparatus includes: a first die including a first switch circuit that …

Memory controller and method of data bus inversion using an error detection correction code

FA Ware, JE Linstadt - US Patent 10,505,565, 2019 - Google Patents
Memory controllers, devices and associated methods are disclosed. In one embodiment, a
memory controller includes write circuitry to transmit write data to a memory device, the write …

Memory controller and method of data bus inversion using an error detection correction code

FA Ware, JE Linstadt - US Patent 11,683,050, 2023 - Google Patents
US11683050B2 - Memory controller and method of data bus inversion using an error detection
correction code - Google Patents US11683050B2 - Memory controller and method of data bus …