Current status and challenges of aggressive equivalent-oxide-thickness (EOT) scaling of
high-κ gate dielectrics via higher-κ (> 20) materials and interfacial layer (IL) scavenging …

For the first time, a leading edge 7nm CMOS platform technology for mobile SoC
applications is presented. This technology provides> 3.3 X routed gate density and 35%∼ …

We have proposed and investigated a super steep subthreshold slope transistor by
introducing negative capacitance of a ferroelectric HfO 2 gate insulator to a vertical tunnel …

This paper presents a comprehensive full-scale three-dimensional simulation scaling study
of the statistical threshold-voltage variability in bulk high-k/metal gate (HKMG) MOSFETs …

Hafnium oxynitride (HfO x N y) gate dielectric was prepared using reactive sputtering
followed by postdeposition annealing at 650° C in a N 2 ambient. Nitrogen incorporation in …

7nm CMOS FinFET technology featuring EUV lithography, 4 th gen. dual Fin and 2 nd gen.
multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total …

This book begins with the premise that energy demands are directing scientists towards ever-
greener methods of power management, so highly integrated power control ICs (integrated …

According to Moore's Law, not only does the number of transistors in an integrated circuit
double every two years, but transistor size also decreases at a predictable rate. At the rate …

NBTI and PBTI are studied in IL/HK/MG gate stacks having EOT down to~ 6Å and fabricated
using low T RTP based thermal IL and a novel IL/HK integration. At equivalent EOT …

Vt instability caused by grain-boundary trap (GBT) in the poly-crystalline silicon (poly-Si)
channel of a 3D NAND string are comprehensively studied. Experimental results reveal that …