Ferroelectric synaptic devices based on CMOS-compatible HfAlO x for neuromorphic and reservoir computing applications
The hafnium oxide-based ferroelectric tunnel junction (FTJ) has been actively researched
because of desirable advantages such as low power and CMOS compatibility to operate as …
because of desirable advantages such as low power and CMOS compatibility to operate as …
Numerical investigations of nanowire gate-all-around negative capacitance GaAs/InN tunnel FET
We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-
effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation. In the …
effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation. In the …
Performance optimization of high-K GAA-PZT Negative Capacitance FET MFIS Silicon Nanowire for low power RFIC and analog applications
Abstract In this article, Gate-All-Around Lead Zirconate Titanate Negative Capacitance (GAA
PZT-NCFET) based Silicon Nanowire (SiNW) device architecture is investigated for the …
PZT-NCFET) based Silicon Nanowire (SiNW) device architecture is investigated for the …
Current prospects and challenges in negative-capacitance field-effect transistors
MS Islam, AAM Mazumder, C Zhou… - IEEE Journal of the …, 2023 - ieeexplore.ieee.org
For decades, the fundamental driving force behind energy-efficient and cost-effective
electronic components has been the downward scaling of electronic devices. However, due …
electronic components has been the downward scaling of electronic devices. However, due …
[HTML][HTML] Dual source negative capacitance GaSb/InGaAsSb/InAs heterostructure based vertical TFET with steep subthreshold swing and high on-off current ratio
Continuous downscaling of CMOS technology at the nanometer scale with conventional
MOSFETs leads to short channel effects (SCE), increased subthreshold slope (SS), and …
MOSFETs leads to short channel effects (SCE), increased subthreshold slope (SS), and …
TMD material investigation for a low hysteresis vdW NCFET logic transistor
IBM Dason, N Kasthuri, D Nirmal - Semiconductor Science and …, 2024 - iopscience.iop.org
Boltzmann limit is inevitable in conventional MOSFETs, which prevent them to be used for
low-power applications. Research in device physics can address this problem by selection …
low-power applications. Research in device physics can address this problem by selection …
Negative capacitance gate-all-around PZT silicon nanowire with high-K/metal gate MFIS structure for low SS and high I on/I off
In the present work, a high-k dielectric hafnium dioxide and lead zirconate titanate (PZT)
have been incorporated as a ferroelectric (FE) layer in the gate stack. The I on/I off ratio …
have been incorporated as a ferroelectric (FE) layer in the gate stack. The I on/I off ratio …
Temperature analysis of lead zirconate titanate GAA-NCFET nanowire with interface trap charges
V Kumar, RK Maurya, K Mummaneni - Materials Science and Engineering …, 2024 - Elsevier
This article explores the static and trap analysis of lead zirconate titanate negative
capacitance gate-all-around (PZT NC GAAFET) nanowire at different temperature using …
capacitance gate-all-around (PZT NC GAAFET) nanowire at different temperature using …
Analytical Modeling of Epsilon-Near-Zero Effect in Indium Tin Oxide and Its Application as an Optical Modulator
O Qasaimeh - IEEE Transactions on Electron Devices, 2024 - ieeexplore.ieee.org
We present a theoretical model for the complex optical conductivity of a structure consisting
of indium tin oxide (ITO) and hafnium oxide (HfO2). The model includes an analytical …
of indium tin oxide (ITO) and hafnium oxide (HfO2). The model includes an analytical …