An area efficient network on chip architecture using high performance pipelines FIFO technique
S Sariga, C Nandagopal - 2017 IEEE International Conference …, 2017 - ieeexplore.ieee.org
Most correspondence movement in today's Network on Chips (NOC) depends on switch for
unstable memory based outlines. The NOC ought to be intended to effectively deal with the …
unstable memory based outlines. The NOC ought to be intended to effectively deal with the …
[PDF][PDF] Variable Latency Approach in VLSI Adder Implemented to Reduce Area and Power
K Kaarthik, C Vivek - Indian Journal …, 2018 - sciresol.s3.us-east-2.amazonaws …
Abstract Objective: The Ultimate aim of the VLSI Design is to improve the efficiency,
Reduction of Delay and Power Consumption and to minimize the area. In our proposed …
Reduction of Delay and Power Consumption and to minimize the area. In our proposed …
[引用][C] An Effective Low Power High Gain Op-Amp Design for Bio-Medical Application
P Nagarajan, M Srividhya, PG Scholar - Int. J. Pure and Appl. Math, 2018
[引用][C] AN EFFICIENT FPGA IMPLEMENTATION OF THE CLOCK GATED RSFQ MATRIX MULTIPLIER
TN Karur - Turkish Journal of Physiotherapy and Rehabilitation
[引用][C] Design and Implementation of Efficient Encoder and Decoder for Wireless Communication
N Mahendran, A Revathi - Journal of Chemical and Pharmaceutical Sciences …
[引用][C] Performance Comparison in Topological Design of Low Power CMOS Full Adder Circuits
KS Swetha, M Mangaiyarkarasi, M Chitravalavan
[引用][C] Design of Low Power Content-Addressable Memory using Master–Slave Match Line
P Nithya, S Tamilselvan - Journal of Chemical and Pharmaceutical Sciences …