IBM POWER8 circuit design and energy optimization

V Zyuban, J Friedrich, DM Dreps, J Pille… - IBM Journal of …, 2015 - ieeexplore.ieee.org
The IBM POWER8™ processor is a 649-mm, 4.2-billion transistor, high-frequency
microprocessor fabricated in the IBM 22-nm silicon on insulator (SOI) technology with …

IBM z14 design methodology enhancements in the 14-nm technology node

C Berry, J Warnock, J Badar, DG Bair… - IBM Journal of …, 2018 - ieeexplore.ieee.org
In designing the IBM z14 microprocessor chipset, we discarded many of our previous
assumptions and processes in favor of newer, more radical approaches. These new …

POWER8 design methodology innovations for improving productivity and reducing power

MM Ziegler, R Puri, B Philhower… - Proceedings of the …, 2014 - ieeexplore.ieee.org
The design complexity of modern high performance processors calls for innovative design
methodologies for achieving time-to-market goals. New design techniques are also needed …

LatchPlanner: Latch placement algorithm for datapath-oriented high-performance VLSI designs

M Cho, H Xiang, H Ren, MM Ziegler… - 2013 IEEE/ACM …, 2013 - ieeexplore.ieee.org
In this paper, we present a novel algorithm for latch placement, LatchPlanner which enables
a placement engine to deliver high quality placement for datapath-oriented design. Datapath …

Integrated circuits having in-situ constraints

QD Qian - US Patent 10,216,890, 2019 - Google Patents
In accordance with the present method and system for improving integrated circuit layout, a
local process modification is calculated from simulated process response variables at a set …

Hierarchical wire-pin co-optimization

CJ Berry, AKM Chandrasekaran, RJ Darden… - US Patent …, 2017 - Google Patents
(57) ABSTRACT A method and system to perform physical synthesis in a chip design
process using hierarchical wire-pin co-optimization are described. The method includes …

Soft hierarchy-based physical synthesis for large-scale, high-performance circuits

M Cho, AW Ng, R Puri, H Ren, H Xiang… - US Patent …, 2013 - Google Patents
In one embodiment, the invention is a method and apparatus for soft hierarchy-based
synthesis for large-scale, high-performance circuits. One embodiment of a method for …

Machine-learning based datapath extraction

SI Ward - US Patent 8,589,855, 2013 - Google Patents
A datapath extraction tool uses machine-learning models to selectively classify clusters of
cells in an integrated circuit design as either datapath logic or non-datapath logic based on …

Boundary latch and logic placement to satisfy timing constraints

CJ Alpert, MD Aubel, GF Ford, Z Li, CN Sze… - US Patent …, 2015 - Google Patents
Boundary timing in the design of an integrated circuit is facilitated by designating a Subset of
boundary latches in the circuit, and applying placement constraints to the boundary latches …

Layout of large block synthesis blocks in integrated circuits

H Barowski, HD Folberth, J Keinert, S Saha - US Patent 9,910,948, 2018 - Google Patents
Generating a layout of an integrated circuit chip area from a description of an integrated
circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design …