[图书][B] Backspace: Formal analysis for post-silicon debug

FM De Paula, M Gort, AJ Hu, SJE Wilton, J Yang - 2008 - ieeexplore.ieee.org
Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a
new design behaves incorrectly. This problem now consumes over half of the overall …

Low-cost TMR for fault-tolerance on coarse-grained reconfigurable architectures

T Schweizer, P Schlicker, S Eisenhardt… - 2011 International …, 2011 - ieeexplore.ieee.org
Hardware redundancy is a common method for improving the reliability of a system. The
disadvantage of this approach is the hardware overhead and the additional power …

System and methods for generating and managing a virtual device

F Xie, K Cong, L Lei - US Patent 8,666,723, 2014 - Google Patents
Certain embodiments of the present invention are configured to permit development and
validation of a device driver or a device application program by using improved virtual …

Post-silicon conformance checking with virtual prototypes

L Lei, F Xie, K Cong - Proceedings of the 50th Annual Design …, 2013 - dl.acm.org
Virtual prototypes are increasingly used in device/driver co-development and co-validation
to enable early driver development and reduce product time-to-market. However, drivers …

System and methods for generating and managing a virtual device

F Xie, K Cong, L Lei - US Patent 9,152,540, 2015 - Google Patents
Computer systems, such as Smartphones, personal digital assistants, tablets, netbooks,
laptops, and desktops, typically include a processor, communication unit such as a bus …

Using run-time reconfiguration to implement fault-tolerant coarse grained reconfigurable architectures

T Schweizer, A Küster, S Eisenhardt… - 2012 IEEE 26th …, 2012 - ieeexplore.ieee.org
Triple modular redundancy (TMR) is a common method to implement fault-tolerant circuits.
Traditionally, TMR is realized by triplication of components. In order to reduce the area …

Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors

TY Yeh, YN Patt - Proceedings of the 26th Annual International …, 1993 - ieeexplore.ieee.org
Presents a comparison of superscalar and decoupled access/execute architectures. Both
architectures attempt to exploit instruction-level parallelism by issuing multiple instructions …

Integration of hardware assertions in systems-on-chip

J Geuzebroek, B Vermeulen - 2008 IEEE International Test …, 2008 - ieeexplore.ieee.org
Assertions in silicon help post-silicon debug by providing observability of internal properties
within a system which are otherwise hard to observe. Besides generating synthesizable …

Formal-analysis-based trace computation for post-silicon debug

M Gort, FM De Paula, JJW Kuan… - IEEE transactions on …, 2011 - ieeexplore.ieee.org
This paper presents a post-silicon debug methodology that provides a means to rewind, or
backspace, a chip from a known crash state using a combination of on-chip real-time data …

Optimizing post-silicon conformance checking

L Lei, K Cong, F Xie - 2013 IEEE 31st International Conference …, 2013 - ieeexplore.ieee.org
Virtual prototypes of hardware devices, aka, virtual devices, are increasingly used to enable
early software development before silicon prototypes/devices are available. In previous …