A prerequisite of energy-aware scheduling is precise knowledge of any activity inside the
computer system. Embedded hardware monitors (eg, processor performance counters) have …

This paper studies the data locality of the work-stealing scheduling algorithm on hardware-
controlled shared-memory machines. We present lower and upper bounds on the number of …

The major chip manufacturers have all introduced chip multiprocessing (CMP) and
simultaneous multithreading (SMT) technology into their processing units. As a result, even …

Scalability of the core frequency is a common feature of low-power processor architectures.
Many heuristics for frequency scaling were proposed in the past to find the best trade-off …

An increasing number of new multicore systems use the Non-Uniform Memory Access
architecture due to its scalable memory performance. However, the complex interplay …

Multicore processors contain new hardware characteristics that are different from previous
generation single-core systems or traditional SMP (symmetric multiprocessing) …

Currently, parallel platforms based on large scale hierarchical shared memory
multiprocessors with Non-Uniform Memory Access (NUMA) are becoming a trend in …

High performance on multicore processors requires that schedulers be reinvented.
Traditional schedulers focus on keeping execution units busy by assigning each core a …

The running time and memory requirement of a parallel program with dynamic, lightweight
threads depends heavily on the underlying thread scheduler. In this paper, we present a …

In modern data centers, the impact on the thermal properties by increased scale and power
densities is enormous and poses new challenges on the designers of both computing as …