A survey of network-based hardware accelerators

I Skliarova - Electronics, 2022 - mdpi.com
Many practical data-processing algorithms fail to execute efficiently on general-purpose
CPUs (Central Processing Units) due to the sequential matter of their operations and …

High-performance implementation of regular and easily scalable sorting networks on an FPGA

V Sklyarov, I Skliarova - Microprocessors and Microsystems, 2014 - Elsevier
The paper is dedicated to fast FPGA-based hardware accelerators that implement sorting
networks. The primary emphasis is on the uniformity of core components, feasible …

[PDF][PDF] Hardware accelerators for information processing in high-performance computing systems

V Sklyarov, I Skliarova, I Utepbergenov… - … journal of innovative …, 2019 - researchgate.net
A frequent problem in information processing is the rapid extraction and subsequent
analysis of subsets of data that have to be formed from external requests supplying some …

Efficient hamming weight comparators for binary vectors based on accumulative and up/down parallel counters

B Parhami - IEEE Transactions on Circuits and Systems II …, 2009 - ieeexplore.ieee.org
New counting-based methods for comparing the Hamming weight of a binary vector with a
constant, as well as comparing the Hamming weights of two input vectors, are proposed. It is …

Design and implementation of counting networks

V Sklyarov, I Skliarova - Computing, 2015 - Springer
The paper describes Hamming weight counters/comparators built on counting networks that
incorporate two distinctive and important features. The counting networks are composed of …

Accelerating Population Count with a Hardware Co-Processor for MicroBlaze

I Skliarova - Journal of Low Power Electronics and Applications, 2021 - mdpi.com
This paper proposes a Field-Programmable Gate Array (FPGA)-based hardware accelerator
for assisting the embedded MicroBlaze soft-core processor in calculating population count …

[PDF][PDF] High-performance information processing in distributed computing systems

V Sklyarov, A Rjabov, I Skliarova… - International Journal of …, 2016 - ijicic.org
This paper explores distributed computing systems that may be used efficiently in
information processing that is frequently needed in electronic, environmental, medical, and …

Designing efficient codecs for bus-invert berger code for fully asymmetric communication

SJ Piestrak, S Pillement… - iEEE transactions on …, 2010 - ieeexplore.ieee.org
Berger-invert code is a coding scheme proposed recently to protect communication
channels against all asymmetric errors and to decrease power consumption. This brief …

Area-efficient parallel-prefix binary comparator

AK Panda, R Palisetty, KC Ray - 2019 IEEE International …, 2019 - ieeexplore.ieee.org
Binary comparator is the most basic component for comparing the two binary operands in
different arithmetic functional blocks, digital communication and encryption/decryption …

Multi-core DSP-based vector set bits counters/comparators

V Sklyarov, I Skliarova - Journal of Signal Processing Systems, 2015 - Springer
The paper shows that fast counting non-zero components (Hamming weights) and
comparing the results (Hamming distances) in large sets of data items is important for …