Designing custom arithmetic data paths with FloPoCo

F De Dinechin, B Pasca - IEEE Design & Test of Computers, 2011 - ieeexplore.ieee.org
Efficient implementation of basic, data-path circuit elements is of fundamental importance to
achieving high performance in FPGA-based acceleration of scientific computing. This work …

Floating-point exponential functions for DSP-enabled FPGAs

F De Dinechin, B Pasca - 2010 International Conference on …, 2010 - ieeexplore.ieee.org
This article presents a generator of floating-point exponential operators targeting recent
FPGAs with embedded memories and DSP blocks. A single-precision operator consumes …

[图书][B] Multiple constant multiplication optimizations for field programmable gate arrays

M Kumm, P Zipf - 2016 - Springer
As silicon technology advances, field programmable gate arrays appear to gain ground
against the traditional ASIC project starts, reaching out to form the mainstream …

Parameter space for the architecture of FFT-based Montgomery modular multiplication

DD Chen, GX Yao, RCC Cheung… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
Modular multiplication is the core operation in public-key cryptographic algorithms such as
RSA and the Diffie-Hellman algorithm. The efficiency of the modular multiplier plays a crucial …

FPGA-specific arithmetic optimizations of short-latency adders

HD Nguyen, B Pasca… - 2011 21st International …, 2011 - ieeexplore.ieee.org
Integer addition is a pervasive operation in FPGA designs. The need for fast wide adders
grows with the demand for large precisions as, for example, required for the implementation …

Fast and area efficient adder for wide data in recent Xilinx FPGAs

P Källström, O Gustafsson - 2016 26th International Conference …, 2016 - ieeexplore.ieee.org
Most modern FPGAs have very optimised carry logic for efficient implementations of ripple
carry adders (RCA). Some FPGAs also have a six input look up table (LUT) per cell, whereof …

A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs

M Rogawski, E Homsirikamol… - 2014 24th International …, 2014 - ieeexplore.ieee.org
In this paper a novel, low-latency family of high-radix Parallel Prefix Network adders and
modular adders has been proposed. This family efficiently takes advantage of fast carry …

Floating-point exponentiation units for reconfigurable computing

F De Dinechin, P Echeverria, M López-Vallejo… - ACM Transactions on …, 2013 - dl.acm.org
The high performance and capacity of current FPGAs makes them suitable as acceleration
co-processors. This article studies the implementation, for such accelerators, of the floating …

Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs

A Vazquez, F De Dinechin - 2010 International Conference on …, 2010 - ieeexplore.ieee.org
Decimal multiplication is one of the most frequent operations used by many financial,
business and user-oriented applications but current implementations in FPGAs are very …

High precision, high performance FPGA adders

M Langhammer, B Pasca… - 2019 IEEE 27th Annual …, 2019 - ieeexplore.ieee.org
FPGAs are now being commonly used in the datacenter as smart Network Interface Cards
(NICs), with cryptography as one of the strategic application areas. Public key cryptography …