Design of control unit for low power AU using reversible logic

HVR Aradhya, BVP Kumar, KN Muralidhara - Procedia Engineering, 2012 - Elsevier
Reversible Logic is becoming one of the potentialpower optimization techniquesin Low
Power CMOS design, and also finds its application in Quantum Computing and …

Optimised reversible divider circuit

A Bolhassani, M Haghparast - International Journal of …, 2016 - inderscienceonline.com
Reversible logic has received a great deal of attention from many researchers over recent
years for its enormous potential for application in quantum computing and nanotechnology …

Function design for minimum multiple-control Toffoli circuits of reversible adder/subtractor blocks and arithmetic logic units

MB Ali, T Hirayama, K Yamanaka… - IEICE Transactions on …, 2018 - search.ieice.org
In this paper, we propose a design of reversible adder/subtractor blocks and arithmetic logic
units (ALUs). The main concept of our approach is different from that of the existing related …

Area and timing analysis of advanced adders under changing technologies

A Raghunandan, HVR Aradhya - 2019 4th International …, 2019 - ieeexplore.ieee.org
A good VLSI Design is one with low area occupancy and high speed of operation. As per
Moore's law the number of transistors on a chip, increase and so does the overall chip Area …

[PDF][PDF] Reversible architecture of computer arithmetic

S Sultana, K Radecka - International Journal of Computer Applications, 2014 - Citeseer
Reversible logic plays an important role in emerging low power designs and quantum
computing. This paper presents an efficient way to realize reversible arithmetic circuits …

[PDF][PDF] A power efficient gdi technique for reversible logic multiplexer of emerging nanotechnologies

S Sharma, SB Singh, S Akashe - International Journal of …, 2013 - researchgate.net
Reversible logic is becoming one of the best emerging design approaches for future
computation of reversible logic having its more application in low power application. This …

[PDF][PDF] An improved design of a fault tolerant reversible binary parallel multiplier

P Bhardwaj, M Singh - International (IJETR), 2014 - academia.edu
The complexity of hardware is increasing in day by day portable devices. Power is the basic
constraint for any circuit & though for complex hardware the power factor plays vital role …

[PDF][PDF] Design and Optimization of Reversible Carry Look Ahead Adder Circuit

AA Bharadwaj, HR Madan, IK Soares… - International Journal of … - academia.edu
Power dissipation is a prominent factor in limiting the chip area. Conventional computing
has been facing many challenges from the last couple of decades. The device scaling …

[PDF][PDF] Design and Analysis of Low Power Reversible Adder/Subtractor Circuits

A Uma - academia.edu
In recent years, reversible logic has become a promising technology in the areas of low
power VLSI design, nanotechnology, quantum computing and optical computing. The …

A Novel Reversible Adder/Subtractor with Overflow Detection

MR Jahangir, K Navi - Journal of Computational and …, 2016 - ingentaconnect.com
Reversible computation is one of the important theories in the 21st century that has versatile
applications in Nanotechnology, Quantum computing, and low power design. In this paper …