This review paper explores considerations for ultimate CMOS transistor scaling. Transistor
architectures such as extremely thin silicon-on-insulator and FinFET (and related …

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-
induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date …

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length,
strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/CDO for high …

Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive
performance improvements over the past 10 years by incorporating strained silicon (Si) …

An effective way to reduce supply voltage and resulting power consumption without losing
the circuit performance of CMOS is to use CMOS structures using high carrier …

Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub
0.8/Ge/sub 0.2/heterostructures. Epitaxial layer structures were designed to yield well …

Semiconductor industry has increasingly resorted to strain as a means of realizing the
required node-to-node transistor performance improvements. Straining silicon …

An extraordinary combination of material science, manufacturing processes, and innovative
thinking spurred the development of SiGe heterojunction devices that offer a wide array of …

This work looks at past, present, and future material changes for the metal-oxide-
semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk …

We have fabricated strained Ge channel p-type metal–oxide–semiconductor field-effect
transistors (p-MOSFETs) on Si 0.3 Ge 0.7 virtual substrates. The poor interface between …