6.8 A 100Gb/s 1.6 V ppd PAM-8 Transmitter with High-Swing $\mathbf {3+ 1} $ Hybrid FFE Taps in 40nm

A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization

J Jin, SM Lee, K Min, S Ju, J Lim, J Yook… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
This article presents a 16-Gb/s/pin 0.764-pJ/b single-ended four-level pulse-amplitude
modulation (PAM-4) transceiver in a 4-nm CMOS process. A switching-jitter compensation …
被引用次数：11 相关文章 所有 3 个版本

A 102-Gb/s/lane 1.4-Vppd Linear Range PAM-8 Receiver Frontend With Multi-Path Continuous-Time Linear Equalization in 28-nm CMOS

S Lee, H Seo, S Son, S Yeom… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
This brief proposes a 102-Gb/s eight-level pulse amplitude modulation (PAM-8) wireline
receiver frontend system with high linearity. The receiver adopts a strategy wherein the …
被引用次数：1 相关文章

An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation

M Megahed, Y Chun, Z Wang… - IEEE Journal of Solid …, 2024 - ieeexplore.ieee.org
This article presents a novel eight-ary modulation technique with improved signal-to-noise
ratio (SNR) compared to conventional pulse amplitude modulation 8 (PAM-8). The proposed …
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100–112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 1 Hybrid FFE Taps in 40-nm Technology

E Song, J Yang, Y Oh, S Hong, D Lee… - IEEE Journal of Solid …, 2024 - ieeexplore.ieee.org
This article presents two eight-level pulse amplitude modulation (PAM-8) transmitters (TX)
that achieve 100-and 112-Gb/s data rates, and a high output swing of 1.6 peak-to-peak …
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A 36-Gb/s 1.6-pJ/b PAM-3 Transmitter Leveraging Digital Logic Cells and 4-Tap FFE in 22-nm CMOS

PMY Fan, MX Wang, WT Lin… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
The first 36-Gb/s transmitter with differential outputs leveraging the three-level pulse
amplitude modulation (PAM-3) and digital logic cells is investigated in this study. The …
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Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration

T Dickson, Z Deniz, M Cochet… - 2024 IEEE Custom …, 2024 - ieeexplore.ieee.org
DAC-based wireline transmitters are a critical component of wireline electrical links
operating above 100 Gb/s. As systems explore the use of more sophisticated modulation …
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A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology

Y Oh, H Im, J Yang, E Song, D Lee… - … on Circuits and …, 2024 - ieeexplore.ieee.org
This paper presents a 100-Gb/s eight-level pulse amplitude modulation (PAM-8) transmitter
(TX) for next-generation wireline communication systems. The high-swing hybrid driver …
被引用次数：2 相关文章

A Single-Ended Duobinary-PAM4 (PAM7) Transmitter With a 2-Tap Feed-Forward Equalizer

S Park, J Kim, J Park, J Bae… - IEEE Solid-State Circuits …, 2023 - ieeexplore.ieee.org
A dual-mode transmitter, capable of both pulse amplitude modulation 4-level (PAM4) and
duobinary-PAM4 signal generation, has been demonstrated in a 28-nm CMOS technology …
被引用次数：4 相关文章 所有 2 个版本

An Analysis of Current-mode Drivers in 40-nm CMOS Technology

B Lim, H Jo, J Han - 2023 20th International SoC Design …, 2023 - ieeexplore.ieee.org
This paper compares two prominent high-speed link transmitter driver topologies, cascode
current-mode logic (CML) and tailless CML, exploring their design tradeoffs. Analysis and …
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A 24-Gb/s PAM-4 Tailless Current-mode Driver with Output Impedance Enhancing Technique in 14-nm FinFET

Y Jo, J Han - JOURNAL OF SEMICONDUCTOR TECHNOLOGY …, 2024 - dbpia.co.kr
This paper presents a four-level pulse amplitude modulation (PAM-4) transmit driver utilizing
the tailless current-mode structure. The PAM-4 driver operates at 24 Gb/s with a 1.3-V supply …
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