A 3-D-integrated silicon photonic microring-based 112-Gb/s PAM-4 transmitter with nonlinear equalization and thermal control

H Li, G Balamurugan, T Kim, MN Sakib… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
Microring modulators (MRMs) with CMOS electronics enable compact low power transmitter
solutions for 400G Ethernet and co-packaged optical transceivers. In this article, we present …

Linearized Analysis and Quantization Error Minimization for Mid-Rise TDCs: A Tutorial

X Wang, MP Kennedy - … Transactions on Circuits and Systems I …, 2025 - ieeexplore.ieee.org
The mid-rise time-to-digital converter (TDC), eg, a binary (bang-bang) phase detector and
other few-bit TDCs, is commonly used as the phase detector (PD) in a digital phase locked …

Silicon photonic microring-based 4× 112 Gb/s WDM transmitter with photocurrent-based thermal control in 28-nm CMOS

J Sharma, Z Xuan, H Li, T Kim, R Kumar… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This work presents a hybrid-integrated 4-micro-ring modulator-based wavelength-division
multiplexed (WDM) optical transmitter (OTX) in the O-band, suitable for co-packaged optics …

A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter

M Mercandelli, A Santiccioli, A Parisi… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …

A 0.65-V 12–16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM

Z Zhang, G Zhu, CP Yue - IEEE Journal of Solid-State Circuits, 2020 - ieeexplore.ieee.org
This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …

A comprehensive phase noise analysis of bang-bang digital PLLs

L Avallone, M Mercandelli, A Santiccioli… - … on Circuits and …, 2021 - ieeexplore.ieee.org
This work introduces an accurate linearized model and phase noise spectral analysis of
digital bang-bang PLLs, that includes both the reference and the digitally-controlled …

A harmonic-mixing PLL architecture for millimeter-wave application

D Yang, D Murphy, H Darabi, A Behzad… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
A low-noise synthesizer design in the millimeter-wave (mm-wave) range is complicated by
the invariably large closed-loop gain and the high operation frequency of the voltage …

Reference oversampling PLL achieving− 256-dB FoM and− 78-dBc reference spur

JH Seol, K Choo, D Blaauw… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This article presents a low jitter, low power, low reference spur LC oscillator-based reference
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …

Impedance-based prediction of distortions generated by resonance in grid-connected converters

S Shah, L Parsa - IEEE Transactions on Energy Conversion, 2019 - ieeexplore.ieee.org
Small-signal impedance-based analysis can effectively predict the frequency and damping
of resonance modes in power electronic systems. However, it cannot predict the magnitude …

A sub-100 fs-jitter 8.16-GHz ring-oscillator-based power-gating injection-locked clock multiplier with the multiplication factor of 68

S Park, S Yoo, Y Shin, J Lee… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This work presents an ultralow-jitter ring-oscillator (RO)-based injection-locked clock
multiplier (ILCM). Using the power-gating (PG) injection method that can completely remove …