A low-power 10 to 15 Gb/s common-gate CTLE based on optimized active inductors
A new low-power common-gate continuous-time linear equalizer (CG-CTLE) is presented
that exploits active matching termination to increase power efficiency. Also., a new active …
that exploits active matching termination to increase power efficiency. Also., a new active …
0.058 mm2 13 Gbit/s inductorless analogue equaliser with low‐frequency equalisation compensating 15 dB channel loss
A Balachandran, Y Chen, P Choi… - Electronics Letters, 2018 - Wiley Online Library
An inductorless 13 Gbit/s analogue equaliser with an additional low‐frequency equalisation
(LFEQ) to counter the low‐frequency channel losses is presented. An active feedback …
(LFEQ) to counter the low‐frequency channel losses is presented. An active feedback …
A high efficient CTLE for 12.5 Gbps receiver of JESD204B standard
G Chen, M Gong, D Fu, J Zhang - IEICE Electronics Express, 2018 - jstage.jst.go.jp
A 12.5 Gbps continuous-time linear equalizer circuit (CTLE) constructed with two stage
equalizer, three stages of limiting amplifier and designed in 55nm CMOS technology for high …
equalizer, three stages of limiting amplifier and designed in 55nm CMOS technology for high …
[PDF][PDF] 采用自适应连续时间线性均衡器和判决反馈均衡器算法的一种16 Gbit/s 并转串/串转并接口
文溢， 陈建军， 黄俊， 姚啸虎， 刘衡竹 - 电子与信息学报, 2023 - jeit.ac.cn
该文在体硅CMOS 工艺下设计了一种16 Gbit/s 并转串/串转并接口(SerDes) 芯片, 该SerDes
由4 个通道(lanes) 和2 个锁相环(PLLs) 组成. 在接收器模拟前端(AFE) 采用负阻抗结构连续时间 …
由4 个通道(lanes) 和2 个锁相环(PLLs) 组成. 在接收器模拟前端(AFE) 采用负阻抗结构连续时间 …
A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces
This brief presents a 10~Gb/s low-power single-ended linear equalizer for DRAMM
interfaces in 12nm FinFET technology. The proposed architecture consists of a continuous …
interfaces in 12nm FinFET technology. The proposed architecture consists of a continuous …
A 16 Gbit/s Serializer/Deserializer with Adaptive Continuous Time Linear Equalizer and Decision Feedback Equalizer Equalization Algorithm
Y WEN, J CHEN, J HUANG, X YAO, H LIU - 电子与信息学报, 2023 - jeit.ac.cn
Abstract A 16 Gbit/s Serializer/Deserializer interface (SerDes) chip which is composed of 4
lanes and 2 Phase-Locked Loop (PLLs), is designed in bulk CMOS technology. A negative …
lanes and 2 Phase-Locked Loop (PLLs), is designed in bulk CMOS technology. A negative …
A 10-Gbps CTLE design using split-length input pair MOS Transistors
A Shehata, GA Fahmy, HF Ragai - International Journal of …, 2023 - Taylor & Francis
The equaliser is an indispensable block inside the receiver in Serial Link systems. It is used
to moderate the high-frequency loss of the signal in the channel. A new technique is …
to moderate the high-frequency loss of the signal in the channel. A new technique is …
A Novel Three-Stage CTLE Circuit for 12.5 Gbps SerDes
Z Yang, L Chen, J Zhang, M Chen… - 2024 4th International …, 2024 - ieeexplore.ieee.org
We proposed a novel three-stage CTLE circuit for 12.5 Gbps SerDes based on 28nm CMOS
process. A cross-coupled negative capacitance structure was adopted to feature more zero …
process. A cross-coupled negative capacitance structure was adopted to feature more zero …
An accurate peak and noise model of CTLE applied to the front end of CLKRX
S Tao, T Sun, K Wu, J Li, N Ning… - 2022 IEEE 16th …, 2022 - ieeexplore.ieee.org
In this paper, an accurate peak and noise analytic model is presented by analyzing the
transfer function of a continuous-time linear equalization (CTLE) circuit with band-pass …
transfer function of a continuous-time linear equalization (CTLE) circuit with band-pass …
Energy and area efficient mixed-mode MCMC MIMO detector
A Aghighi, B Farhang-Boroujeny… - 2020 IFIP/IEEE 28th …, 2020 - ieeexplore.ieee.org
A hybrid analog/digital signal processor has been proposed to implement energy-efficient
multi-input-multi-output (MIMO) detectors. A sub-optimum MIMO detector based on Markov …
multi-input-multi-output (MIMO) detectors. A sub-optimum MIMO detector based on Markov …