RAIDed memory system
JCR Bennett, DM Smith, DC Biederman - US Patent 9,335,939, 2016 - Google Patents
A memory system and a method for managing the system is described. The system is
configured such a plurality of system controllers, which may be RAID controllers, receive …
configured such a plurality of system controllers, which may be RAID controllers, receive …
Method for dependency broadcasting through a source organized source view data structure
M Abdallah - US Patent 10,275,255, 2019 - Google Patents
(57) ABSTRACT A method for dependency broadcasting through a source organized source
view data structure. The method includes receiving an incoming instruction sequence using …
view data structure. The method includes receiving an incoming instruction sequence using …
Hybrid block-based processor and custom function blocks
AL Smith, JS Gray - US Patent 11,449,342, 2022 - Google Patents
Apparatus and methods are disclosed for implementing block-based processors having
custom function blocks, including field-programmable gate array (FPGA) implementations. In …
custom function blocks, including field-programmable gate array (FPGA) implementations. In …
Block-based processor core composition register
Abstract Systems, apparatuses, and methods related to a block-based processor core
composition register are disclosed. In one example of the disclosed technology, a processor …
composition register are disclosed. In one example of the disclosed technology, a processor …
Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
M Abdallah - US Patent 9,990,200, 2018 - Google Patents
A method for executing instructions using a plurality of virtual cores for a processor. The
method includes receiving an incoming instruction sequence using a global front end …
method includes receiving an incoming instruction sequence using a global front end …
Memory system management
JCR Bennett, DC Biederman, DM Smith - US Patent 9,417,823, 2016 - Google Patents
(57) ABSTRACT A memory system and a method for managing the system is described. The
system is configured such a plurality of system controllers, which may be RAID controllers …
system is configured such a plurality of system controllers, which may be RAID controllers …
Accelerated code optimizer for a multiengine microprocessor
M Abdallah - US Patent 10,191,746, 2019 - Google Patents
(57) ABSTRACT A method for accelerating code optimization a micropro cessor. The
method includes fetching an incoming microin struction sequence using an instruction fetch …
method includes fetching an incoming microin struction sequence using an instruction fetch …
Data multicasting with router replication and target instruction identification in a distributed multi-core processing architecture
Methods, procedures, apparatuses, computer programs, computer-accessible mediums,
processing arrangements and systems generally related to data multi-casting in a distributed …
processing arrangements and systems generally related to data multi-casting in a distributed …
Combined branch target and predicate prediction
DC Burger, SW Keckler - US Patent 9,703,565, 2017 - Google Patents
Embodiments provide methods, apparatus, systems, and computer readable media
associated with predicting predicates and branch targets during execution of programs …
associated with predicting predicates and branch targets during execution of programs …
Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
Abstract Systems, apparatuses, and methods related to a block-based processor core
topology register are disclosed. In one example of the disclosed technology, a processor …
topology register are disclosed. In one example of the disclosed technology, a processor …