Addressing manufacturing challenges with cost-efficient fault tolerant routing
The high-performance computing domain is enriching with the inclusion of Networks-on-chip
(NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the …
(NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the …
Cost-efficient on-chip routing implementations for CMP and MPSoC systems
The high-performance computing domain is enriching with the inclusion of networks-on-chip
(NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the …
(NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the …
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs
A Ghiribaldi, D Ludovici, F Trivino, A Strano… - ACM Transactions on …, 2013 - dl.acm.org
Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An
effective testing and configuration strategy however implies two opposite requirements. One …
effective testing and configuration strategy however implies two opposite requirements. One …
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration
Extending the principle of partially good die allowance to manycore processors, and testing
them over time to detect the onset of permanent faults, are only feasible through proper …
them over time to detect the onset of permanent faults, are only feasible through proper …
System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic
A Ghiribaldi, D Ludovici, M Favalli… - 2011 IEEE/IFIP 19th …, 2011 - ieeexplore.ieee.org
Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An
effective testing and configuration strategy however implies two opposite requirements. On …
effective testing and configuration strategy however implies two opposite requirements. On …
An efficient network-on-chip yield estimation approach based on gibbs sampling
A network-on-chip (NoC), a redundancy-rich and thus relatively robust system-chip, is still
vulnerable to defects due to its large-scale integration. Thus, it is desirable to analyze the …
vulnerable to defects due to its large-scale integration. Thus, it is desirable to analyze the …
[PDF][PDF] A survey of logic based distributed routing for on-chip interconnection networks
N Choudhary, CM Samota - International Journal of Soft …, 2013 - researchgate.net
The availability of increased number of resources on a single silicon chip is enforcing the
designers to come up with mechanisms for efficient and effective management of these …
designers to come up with mechanisms for efficient and effective management of these …
Bandwidth Improvement Using Slotted Triangular MPA
TR Chanu, S Rawat - 2013 Third International Conference on …, 2013 - ieeexplore.ieee.org
In this paper a new geometry of Slotted Triangular MPA (Micro strip Patch Antenna) is
proposed with improved Bandwidth from 2.69% to 10.27% at the range of 4.9 GHz to 5.4 …
proposed with improved Bandwidth from 2.69% to 10.27% at the range of 4.9 GHz to 5.4 …
An efficient, low-cost routing framework for convex mesh partitions to support virtualization
At the core of an efficient chip multiprocessors (CMP) is support for unicast and multicast
routing, low implementation costs, and the ability to isolate concurrent applications with …
routing, low implementation costs, and the ability to isolate concurrent applications with …
Cost Effective Routing Implementations for On-chip Networks
S Rodrigo Mocholi - 2010 - riunet.upv.es
Arquitecturas de múltiples núcleos como multiprocesadores (CMP) y soluciones
multiprocesador para sistemas dentro del chip (MPSoCs) actuales se basan en la eficacia …
multiprocesador para sistemas dentro del chip (MPSoCs) actuales se basan en la eficacia …