Difference decision diagrams

J Møller, J Lichtenberg, HR Andersen… - Computer Science Logic …, 1999 - Springer
This paper describes a newdata structure, difference decision diagrams (DDDs), for
representing a Boolean logic over inequalities of the form xy≤ c where the variables are …

[PDF][PDF] An introduction to asynchronous circuit design

A Davis, SM Nowick - The Encyclopedia of Computer Science and …, 1997 - Citeseer
The purpose of this monograph is to provide both an introduction to eld of asynchronous
digital circuit design and an overview of the practical state of the art in 1997. In the early …

Exploitation of different types of locality for web caches

G Karakostas, DN Serpanos - Proceedings ISCC 2002 Seventh …, 2002 - ieeexplore.ieee.org
Object access distribution in the Web is governed by Zipf's law, in general. This property
leads to effective Web caches, which store the most popular objects and typically employ the …

Modeling and designing heterogeneous systems

F Balarin, L Lavagno, C Passerone… - … and Hardware Design …, 2002 - Springer
We present the modeling mechanism employed in Metropolis, a design environment for
heterogeneous embedded systems, and a design methodology based on the mechanism …

Fully symbolic model checking of timed systems using difference decision diagrams

J Møller, J Lichtenberg, HR Andersen… - Electronic Notes in …, 2001 - Elsevier
Current approaches for analyzing timed systems are based on an explicit enumeration of the
discrete states and thus these techniques are only capable of analyzing systems with a …

Verification of timed systems using POSETs

W Belluomini, CJ Myers - … Conference, CAV'98 Vancouver, BC, Canada …, 1998 - Springer
This paper presents a new algorithm for efficiently verifying timed systems. The new
algorithm represents timing information using geometric regions and explores the timed …

Timed state space exploration using posets

W Belluomini, CJ Myers - IEEE Transactions on Computer …, 2000 - ieeexplore.ieee.org
This paper presents a new timing analysis algorithm for efficient state space exploration
during the synthesis of timed circuits or the verification of timed systems. The source of the …

Verification of delayed-reset domino circuits using ATACS

W Belluomini, CJ Myers… - … Symposium on Advanced …, 1999 - ieeexplore.ieee.org
This paper discusses the application of the timing analysis tool ATACS to the high
performance, self-resetting and delayed-reset domino circuits being designed at IBM's …

[图书][B] Encyclopedia of Computer Science and Technology: Volume 38-Supplement 23: Algorithms for Designing Multimedia Storage Servers to Models and …

A Kent, JG Williams - 2021 - taylorfrancis.com
Volume 38-Supplement 23: Algorithms for Designing Multimedia Storage Servers to Models
and Architectures. Covering more than basic computer commands and procedures, this …

[PDF][PDF] Specification and compilation of timed systems

H Zheng - 1998 - researchgate.net
This thesis presents a framework for the speci cation and compilation of modules in a system
that uses di erent synchronization paradigms. These timed systems are described by using …