Challenges and future scope of gate-all-around (GAA) transistors: Physical insights of device-circuit interactions
S Srivastava, A Acharya - Device Circuit Co-Design Issues in FETs, 2024 - taylorfrancis.com
Undoubtedly, FinFET technology is the slogger of today's semiconductor world. However,
the demand for further scaling with a desire for ultra-low-power and high-speed applications …
the demand for further scaling with a desire for ultra-low-power and high-speed applications …
A Novel Capacitorless 1T DRAM with Embedded Oxide Layer
D Zhao, Z Xia, T Yang, Y Yang, W Zhou, Z Huo - Micromachines, 2022 - mdpi.com
A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for
capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively …
capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively …
[HTML][HTML] Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield
K Sakui, Y Li, M Kakumu, K Kanazawa… - … , Devices, Circuits and …, 2023 - Elsevier
TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1
(Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) …
(Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) …
[引用][C] A Novel Capacitorless 1T DRAM with Embedded Oxide Layer. Micromachines 2022, 13, 1772
D Zhao, Z Xia, T Yang, Y Yang, W Zhou, Z Huo - 2022 - europepmc.org
A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for
capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively …
capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively …