Closed-form expressions of the parasitic insulator capacitance and the substrate
capacitance for tapered through-silicon vias (T-TSVs) are proposed. The expressions are …

Through-silicon-via (TSV) enables vertical connectivity between stacked chips or interposer
and is a key technology for 3-D integrated circuits (ICs). While arrays of TSVs are needed in …

Typical 3D integrated circuit structures based on through-silicon vias (TSVs) are complicated
to study and analyze. Therefore, it seems important to find some methods to investigate …

The 3-D multistrata integration puts forward high requirements for signal integrity. The
shielded-pair through-silicon vias (SPTSVs) proposed in this paper feature superior …

This letter presents a new wideband equivalent circuit model for through silicon via (TSV)
with consideration of the effective substrate current loop in silicon substrate and proximity …

Ioannis Savidis was born in Rochester, New York in December 1982. He received the BSE
degree in electrical and computer engineering and biomedical engineering from Duke …

Abstract 3D integration is considered to be the most promising solution to overcome
challenges encountered currently in planar technologies. As an emerging technology …

This paper evaluates the capacitance and conductance of the through silicon vias (TSVs)
with consideration of the multilayer media along the vertical direction and different shapes …

Fully depleted silicon-on-insulator (FDSOI) technology boosts the opportunity to make 3-D
ICs with ultrahigh integration density, due to the short and tiny through-oxide vias (TOVs) …

In this paper, two intelligent methods which are GAs and PSO are used to model noise
coupling in a Three‐Dimensional Integrated Circuit (3D‐IC) based on TSVs. These …