Energy-efficient design methodologies: High-performance VLSI adders

BR Zeydel, D Baran… - IEEE Journal of solid-state …, 2010 - ieeexplore.ieee.org
Energy-efficient design requires exploration of available algorithms, recurrence structures,
energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In …

Designing of low-power data oriented adders

I Brzozowski, A Kos - Microelectronics Journal, 2014 - Elsevier
The paper presents an idea of designing of low-power adders addressed to specific data
processing. Mainly, the idea consists in proper choosing of 1-bit full adder cells for given …

Comparison of performance of high speed VLSI adders

AN Jayanthi, CS Ravichandran - … International Conference on …, 2013 - ieeexplore.ieee.org
In modern VLSI design, the occurrence of delays is predictable. Many digital systems that
process data may have delays. Design requires thorough understanding of algorithms …

Physical vs. physically-aware estimation flow: case study of design space exploration of adders

I Ratkovic, O Palomar, M Stanic, O Unsal… - 2014 IEEE Computer …, 2014 - ieeexplore.ieee.org
Selecting an appropriate estimation method for a given technology and design is of crucial
interest as the estimations guide future project and design decisions. The accuracy of the …

Switching activity calculation of VLSI adders

D Baran, M Aktan, H Karimiyan… - 2009 IEEE 8th …, 2009 - ieeexplore.ieee.org
Using exact switching activity rates at all internal nodes when calculating energy of digital
circuits is believed to result in improved accuracy over to the use of average switching …

A systematic design of novel energy efficient 64 bit parallel prefix adder

N Jagadeeshkumar - 2021 - shodhganga.inflibnet.ac.in
The very large scale integration technology (VLSI) is extensively used in the most of the
emerging field like telecommunication, signal processing, consumer electronics and …

Optimal transistor sizing and voltage scaling for minimal energy use at fixed performance

VG Oklobdzija, M Aktan, D Baran - 2012 Argentine School of …, 2012 - ieeexplore.ieee.org
This paper presents a simple sizing method for low-power that is comparable in speed and
simplicity to the Logical Effort sizing. Yet, the accuracy of the results is in the range of …

[PDF][PDF] Design and implementation of hybrid cascaded energy Efficient Kogge Stone Adder

J Vignesh, E Gajendran, S Khan, N Balakumar… - 2006 - researchgate.net
Addition plays a vital role in all arithmetic operations. It is used widely in many VLSI systems
such as application specific DSP architecture and microprocessor architecture. The energy …

Foreign Direct Investments by Japanese Manufacturers in Vietnam-Domestic Management and Collaboration

L Chun-Wei, WZ Min - 2010 International Conference on …, 2010 - ieeexplore.ieee.org
This research has described and explored the collaborative relationships between foreign
direct investments by Japanese manufacturers in Vietnam and domestic suppliers, how the …

[图书][B] Exploration of energy efficient design methodologies: High performance VLSI adders

D Baran - 2009 - search.proquest.com
Energy-efficient design of digital circuits has become an important issue in recent years. In
this work, the energy-efficient design methodologies are explored in 65nm, 45nm, 32nm and …