Vertically integrated circuits (3-D ICs) may revitalize Moore's law scaling which has slowed
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …

The concept of 3D chip stacks has been advocated by both industry and academia for many
years, and hailed as one of the most promising approaches to meet ever-increasing …

Traditional die-to-die (DTD) clock skew compensation topologies prerequisite matched
delay lines or equal through-silicon via (TSV) delays. Unlike previous techniques, the …

In this paper the design of a novel IP for 3D IC die-to-die clock synchronization is presented.
The proposed design offers notable benefits over the conventional dual DLL based …

Three-dimensional integration is considered to be a promising technology to tackle the
global interconnect scaling problem for terascale integrated circuits (ICs). Three …

Ongoing advancements in 3-D manufacturing are enabling 3-D ICs to contain several
processing cores, hardware accelerators, and dedicated peripherals. Most of these …

We propose efficient algorithms to construct a low-power clock tree for through-silicon-via
(TSV)-based 3D-ICs. We use shutdown gates to save clock trees' dynamic power, which …

The recent advancement in nanotechnology over a different scope of industries and an
expanded microelectronics market demand for low power, high performance and complexity …

Delay units play an important role in bitline design for on-chip memory. Traditional delay
units can be categorized into two types: passive ones and active ones. In this paper, a novel …

This chapter reviews the state-of-the-art design methodologies for TSV-based 3D clock
networks and covers four ingredients:(1) the synthesis flows of basic 3D clock trees in …