Versa: A 36-core systolic multiprocessor with dynamically reconfigurable interconnect and memory
We present Versa, an energy-efficient 36-core systolic multiprocessor with dynamically
reconfigurable interconnects and memory. Versa leverages reconfigurable functional units …
reconfigurable interconnects and memory. Versa leverages reconfigurable functional units …
Computationally-efficient voice activity detection based on deep neural networks
Voice activity detection (VAD) is among the first preprocessing steps in most speech
processing applications. While there are several very low-power analog solutions, the more …
processing applications. While there are several very low-power analog solutions, the more …
Exploiting Reconfiguration and Co-Design for Domain-Agnostic Hardware Acceleration
S Kim - 2023 - deepblue.lib.umich.edu
Hardware accelerators have become permanent features in the post-Dennard computing
landscape, displacing conventional processors for a variety of applications. Not only have …
landscape, displacing conventional processors for a variety of applications. Not only have …
Improving Energy Efficiency of Convolutional Neural Networks on Multi-core Architectures through Run-time Reconfiguration
Convolutional neural networks (CNNs) are built with convolution layers which account for
most of their computation time. The differences in the convolution kernel types (2D, point …
most of their computation time. The differences in the convolution kernel types (2D, point …
Optimizing Sparse Linear Algebra on Reconfigurable Architecture
DH Park - 2021 - deepblue.lib.umich.edu
The rise of cloud computing and deep machine learning in recent years have led to a
tremendous growth of workloads that are not only large, but also have highly sparse …
tremendous growth of workloads that are not only large, but also have highly sparse …