Performance-Driven Analog Layout Automation: Current Status and Future Directions

P Xu, J Li, TY Ho, B Yu, K Zhu - 2024 29th Asia and South …, 2024 - ieeexplore.ieee.org
Optimizing circuit performance presents a pivotal challenge in the realm of automatic analog
physical design. The intricacy of analog performance arises from its sensitivity to layout …

An Open-Source AMS Circuit Optimization Framework Based on Reinforcement Learning-From Specifications to Layouts

Z Li, AC Carusone - IEEE Access, 2024 - ieeexplore.ieee.org
This paper presents a fully open-sourced AMS integrated circuit optimization framework
based on reinforcement learning (RL). Specifically, given a certain circuit topology and …

Compact Single-Ended Transceivers Demonstrating Flexible Generation of 1/N-Rate Receiver Front-Ends for Short-Reach Links

M Lee, J Cho, J Choi, WJ Choi, J Lee… - … on Circuits and …, 2023 - ieeexplore.ieee.org
This paper presents compact single-ended wireline transceivers with software-generated
receiver front-ends. The developed software framework significantly shortens the physical …

AI-EDA: toward a holistic approach to AI-powered EDA

Y Shin - 2023 ACM/IEEE 5th Workshop on Machine Learning …, 2023 - ieeexplore.ieee.org
AI or ML has been extensively studied in CAD and EDA. The number of papers under this
topic, published in major conference proceedings and journals between 2016 and 2020 …

Interactive and Automatic Generation of Primitive Custom Circuit Layout Using LLMs

G You, Y Byun, S Lim, J Han - arXiv preprint arXiv:2408.07279, 2024 - arxiv.org
In this study, we investigate the use of Large Language Models (LLMs) for the interactive
and automated production of customs circuit layouts described in natural language. Our …

A Unified Analysis of Continuous-Time A/D Converters

F Feyling, H Malmberg, C Wulff, T Ytterdal - Authorea Preprints, 2024 - techrxiv.org
As a generalization of the continuous-time pipeline (CTP), we present a theoretical model
that can be used to analyze any conventional continuous-time (CT) analog-to-digital …

Multi-Phase Frequency Divider Generator with Process-Independent Automation

J Jang, H Jeong, J Han - 2023 20th International SoC Design …, 2023 - ieeexplore.ieee.org
This work presents an automatic circuit generator for multi-phase frequency dividers. The
schematic and layout generator scripts are parameterized, allowing users to customize the …

[PDF][PDF] Layout generation using simulated annealing and A

J De Schepper - 2024 - libstore.ugent.be
The author gives permission to make this master dissertation available for consultation and
to copy parts of this master dissertation for personal use. In all cases of other use, the …