A simple power-analysis (SPA) attack on implementations of the AES key expansion
S Mangard - Information Security and Cryptology—ICISC 2002: 5th …, 2003 - Springer
This article presents a simple power-analysis (SPA) attack on implementations of the AES
key expansion. The attack reveals the secret key of AES software implementations on smart …
key expansion. The attack reveals the secret key of AES software implementations on smart …
All the AES you need on Cortex-M3 and M4
P Schwabe, K Stoffelen - International Conference on Selected Areas in …, 2016 - Springer
This paper describes highly-optimized AES-{128,192,256\}-CTR assembly implementations
for the popular ARM Cortex-M3 and M4 embedded microprocessors. These …
for the popular ARM Cortex-M3 and M4 embedded microprocessors. These …
The design of scalar AES instruction set extensions for RISC-V
B Marshall, GR Newell, D Page… - Cryptology ePrint …, 2020 - eprint.iacr.org
Secure, efficient execution of AES is an essential requirement on most computing platforms.
Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a …
Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a …
Security evaluation of DPA countermeasures using dual-rail pre-charge logic style
D Suzuki, M Saeki - … on Cryptographic Hardware and Embedded Systems, 2006 - Springer
In recent years, some countermeasures against Differential Power Analysis (DPA) at the
logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a …
logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a …
New AES software speed records
DJ Bernstein, P Schwabe - Progress in Cryptology-INDOCRYPT 2008: 9th …, 2008 - Springer
This paper presents new speed records for AES software, taking advantage of (1)
architecture-dependent reduction of instructions used to compute AES and (2) …
architecture-dependent reduction of instructions used to compute AES and (2) …
Instruction set extensions for efficient AES implementation on 32-bit processors
S Tillich, J Großschädl - … Hardware and Embedded Systems-CHES 2006 …, 2006 - Springer
Secure communication over public networks like the Internet requires the use of
cryptographic algorithms as basic building blocks. Most cryptographic workloads pose a …
cryptographic algorithms as basic building blocks. Most cryptographic workloads pose a …
OpenCL-based design methodology for application-specific processors
PO Jäskeläinen, CS de La Lama… - 2010 International …, 2010 - ieeexplore.ieee.org
OpenCL is a programming language standard which enables the programmer to express
the application by structuring its computation as kernels. The OpenCL compiler is given the …
the application by structuring its computation as kernels. The OpenCL compiler is given the …
Efficient parallelism of post-quantum signature scheme SPHINCS
SPHINCS was recently proposed as a stateless, quantum-resilient hash-based signature
scheme. However, one possible limitation of SPHINCS is its signing speed, namely, the best …
scheme. However, one possible limitation of SPHINCS is its signing speed, namely, the best …
Side-channel analysis of cryptographic software via early-terminating multiplications
The design of embedded processors demands a careful trade-off between many conflicting
objectives such as performance, silicon area and power consumption. Finding such a trade …
objectives such as performance, silicon area and power consumption. Finding such a trade …
Design and evaluation of a reconfigurable ECU architecture for secure and dependable automotive CPS
The next generation of automobiles integrate a multitude of electronic control units (ECUs) to
implement various automotive control and infotainment applications. However, recent works …
implement various automotive control and infotainment applications. However, recent works …