This paper presents a referenceless baud-rate clock and data recovery (CDR) incorporated
with a continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer …

Improving the energy efficiency of computer communication is becoming more and more
important as the world is creating a massive amount of data, while the interface has been a …

A digitally controlled oscillator (DCO) is presented that utilizes the non-linearity of a resistor-
triode combination in conjunction with a weak latch to mitigate the supply sensitivity of …

This paper investigates the suitability of full duplex simultaneous bidirectional (FD-SBD)
signaling as a method to theoretically double the aggregate data transfer per pin for ultra …

A 2 blind-oversampling, fractionally spaced equalizer (FSE) receiver is presented as an
effective way to combine adaptive equalization and timing recovery in a single control loop …

A bidirectional link geared toward mobile I/O applications is presented that leverages the
technological advantages of CMOS scaling to improve energy efficiency. Active power …

This article presents a clock-domain-based integrated pulsewidth modulation (PWM)(iPWM)
line-coding scheme to enable equalization while operating at low supply voltages. While …

This brief presents a low-cost blind oversampling CDR (Clock Data Recovery) architecture
that obviates the need of a dedicated clock generator or oversampling clock at the receiver …

A rapid growth of data rates in high speed links application makes it difficult to maintain low
bit-error rates (BERs) while communicating data across channels with limited bandwidths …

Phase-locked loops (PLLs) are widely used in communication and digital systems to
generate high frequency clocks by multiplying a low-frequency reference clock. Scaling of …